PLL602-03

Low Phase Noise CMOS XO (48MHz to 100MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3

3. AC Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Crystal Frequency

12

25

MHz

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

ns

Output Clock Duty Cycle

45

50

55

%

4. Jitter and Phase Noise Specification

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

RMS Period Jitter

(1 sigma – 1000 samples)

at 80MHz, with capacitive decoupling

between VDD and GND.

3.5

ps

Phase Noise relative to carrier

80MHz @100Hz offset

-103

dBc/Hz

Phase Noise relative to carrier

80MHz @1kHz offset

-122

dBc/Hz

Phase Noise relative to carrier

80MHz @10kHz offset

-130

dBc/Hz

Phase Noise relative to carrier

80MHz @100kHz offset

-125

dBc/Hz

5. Crystal Specifications

PARAMETERS

SYMBOL

MIN.

TYP.

MAX.

UNITS

Crystal Resonator Frequency

12

25

MHz

Crystal Loading Capacitance Rating

20

pF

Driving power

1

mW

ESR

30

Ω

PACKAGE INFORMATION

C

L

A

8 PIN ( dimensions in mm )

Narrow SOIC

Symbol

Min.

Max.

A

1.47

1.73

A1

0.10

0.25

B

0.33

0.51

C

0.19

0.25

D

4.80

4.95

E

3.80

4.00

H

5.80

6.20

L

0.38

1.27

e

1.27 BSC

E

H

D

A1

e

B

TSSOP

Min.

Max.

-

1.20

0.05

0.15

0.19

0.30

0.09

0.20

2.90

3.10

4.30

4.50

6.20

6.60

0.45

0.75

0.65 BSC