(Preliminary)

PLL500-15/16

Low Phase Noise VCXO (1MHz to 18MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 1

FEATURES

• VCXO with Divider Selection (DIVSEL) input pin

• PLL500-15: ÷8, ÷16

• PLL500-16: ÷2, ÷4

• VCXO output for the 1MHz to 18MHz range

• 16MHz to 36MHz fundamental crystal input.

• Low phase noise (-130 dBc @ 10kHz offset

using a 35.328MHz crystal).

• CMOS output with OE tri-state control.

• Integrated high linearity variable capacitors.

• 12mA drive capability at TTL output.

• ± 150 ppm pull range, max 5% linearity.

• Low jitter (RMS): 2.5ps period jitter.

• 2.5V to 3.3V operation.

RoHS compliant packages, or DIE.

DESCRIPTION

The PLL500-15/16 is a low cost, high performance

and low phase noise VCXO for the 1.0MHz to 18MHz

range, providing less than -130dBc at 10kHz offset

when using a 35.328MHz crystal. The very low jitter

(2.5 ps RMS period jitter) makes this chip ideal for

applications requiring voltage controlled frequency

sources. Input crystal can range from 16MHz to

36MHz (fundamental resonant mode).

PIN CONFIGURATION

DIVIDER SELECTION LOGIC LEVELS

Part #

DivSel State

Operation

1 (Default)

÷16

PLL500-15

0

÷8

1 (Default)

÷4

PLL500-16

0

÷2

BLOCK DIAGRAM

VCON

XIN

VCXO

CLK

Selectable

Divider

Varicap

XOUT

DIVSEL

1

2

3

45

6

7

8

XIN

VCON

DIVSEL^

GND

XOUT

VDD

CLK

OE^

1

2

34

5

6

XOUT

VDD

CLK

XIN

GND

VCON

SOIC-8

SOT23-6*

^: Denotes internal Pull-up

*: SOT package offers single divider option only