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TDA1314T Datasheet(PDF) 4 Page - NXP Semiconductors |
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TDA1314T Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 15 page August 1994 5 Philips Semiconductors Product specification Quadruple filter DAC TDA1314T Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION I2S-bus interface The word select input (pin 26) is connected to the word select line of the I2S-bus interface. This interface has a standard I2S-bus specification as described in the Philips “I2S-bus specification” (ordering number 9398 332 10011). Figure 4 shows an excerpt of the Philips I2S-bus specification interface report with respect to the general timing and format of the I2S-bus. WS logic 0 means left channel word, logic 1 means right channel word. The serial clock input (pin 4) must be in accordance with the I2S-bus specification, i.e. a continuous clock. Serial data front (SDF, pin 25) and serial data rear (SDR, pin 24) are the I2S-bus serial data lines to be processed in the DACs for the loudspeakers of the car (see Fig.2, blocks DACFL and DACFR for the front loudspeakers and blocks DACRL and DACRR for the right loudspeakers). FL stands for Front Left, FR for Front Right, RL for Rear Left and RR for Rear Right. In order to utilize the capabilities of this IC fully, the data word length should be 18 bits. Signals derived from this block are 4 × 18-bit parallel data words which are applied to the 4fs up-sample filters. 4ASF generator SYNTHESIZER SELINPH (pin 3) and WS (pin 26) are the data inputs for this block which generates the FASFDAC, this being the 4fas signal (at 4 times the audio sample frequency), which is used to latch the data words to the DACs and as a reference to the clock generator block for the up-sample filters. It consists of a digital PLL operating at the master clock signal MCLK (pin 5). In normal mode (i.e. in the event that the MCLK signal on pin 5 is a jitter free clock, with a frequency of integer multiples between 45 and 128, of 4 times the frequency of the WS signal) this block is able to generate a jitter free FASFDAC signal for optimum performance of the DAC. This mode is called the free running mode. If, in some applications, there is considerable jitter on the MCLK while WS is more stable (less jitter), the phase-locked mode should be selected. This mode is normally not used and is not recommended. |
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