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PL611S-02 Datasheet(PDF) 4 Page - PhaseLink Corporation

Part No. PL611S-02
Description  1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL611S-02 Datasheet(HTML) 4 Page - PhaseLink Corporation

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(Preliminary)PL611s-02
1.8V-3.3V PicoPLL
TM, World’s Smallest Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 4
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
-0.5
7
V
Input Voltage Range
VI
-0.5
VDD
+0.5
V
Output Voltage Range
VO
-0.5
VDD
+0.5
V
Soldering Temperature (Green package)
260
°C
Data Retention @ 85°C
10
Year
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
-40
85
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Input Frequency (XIN)
Fundamental Crystal
10
50
MHz
@ VDD =3.3V
200
@ VDD =2.5V
166
Input (FIN) Frequency
@ VDD =1.8V
1
133
MHz
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
0.9
VDD
Vpp
Input (FIN) Signal Amplitude
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
0.1
VDD
Vpp
@ VDD =3.3V
200
MHz
@ VDD =2.5V
166
MHz
Output Frequency
@ VDD =1.8V
133
MHz
Settling Time
At power-up (after VDD increases over 1.62V)
2
ms
OE Function; Ta=25º C, 15pF Load
10
ns
Output Enable Time
PDB Function; Ta=25º C, 15pF Load
2
ms
VDD Sensitivity
Frequency vs. VDD +/-10%
-2
2
ppm
Output Rise Time
15pF Load, 10/90% VDD, High Drive, 3.3V
1.2
1.7
ns
Output Fall Time
15pF Load, 90/10% VDD, High Drive, 3.3V
1.2
1.7
ns
Duty Cycle
PLL Enabled, @ VDD /2
45
50
55
%
Period Jitter, Pk-to-Pk*
(measured from 10,000 samples)
With capacitive decoupling between VDD and
GND.
70
ps
* Note: Jitter performance depends on the programming parameters.


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