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PL611S-02 Datasheet(PDF) 3 Page - PhaseLink Corporation

Part No. PL611S-02
Description  1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
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Maker  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL611S-02 Datasheet(HTML) 3 Page - PhaseLink Corporation

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(Preliminary)PL611s-02
1.8V-3.3V PicoPLL
TM, World’s Smallest Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 3
FUNCTIONAL DESCRIPTION
PL611s-02 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-02 accepts a fundamental input crystal of 10MHz to 50MHz or
reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 200MHz. This flexible
design allows the PL611s-02 to deliver any PLL generated frequency, FREF (Crystal or Ref Clk) frequency or
FREF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-02 are mentioned below:
PLL Programming
The PLL in the PL611s-02 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [FOUT = FREF * M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (FVCO/(2*P)),
FREF (Crystal or Ref Clk) output, or FREF/(2*P) output.
The output drive level can be programmed to Low
Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is
determined by the Power Supply Voltage; 200MHz at
3.3V, 166MHz at 2.5V and 133MHz at 1.8V.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-02 to have an
additional clock output programmed to one of the
following:
FREF - Reference (Crystal or Ref Clk) Frequency
FREF / 2
CLK0
CLK0 / 2
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k
pull up
resistor giving a default condition of logic “1”.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-02 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10 A of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-02 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k
pull
up resistor giving a default condition of logic “1”.


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