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SST27VF010-70-3C-WHE Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST27VF010-70-3C-WHE Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
9 / 18 page Preliminary Specifications 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27VF010 / SST27VF020 9 ©2003 Silicon Storage Technology, Inc. S71251-00-000 12/03 AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 0°C to +70°C (Commercial)) Symbol Parameter SST27VF010-70 SST27VF020-70 SST27VF010-90 SST27VF020-90 Units Min Max Min Max TRC Read Cycle Time 70 90 ns TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. CE# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns TCHZ1 CE# High to High-Z Output 25 30 ns TOHZ1 OE# High to High-Z Output 25 30 ns TOH1 Output Hold from Address Change 0 0 ns T9.0 1251 TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS (Ta = 25°C±5°C) Symbol Parameter Min Max Units TCES CE# Setup Time 1 µs TCEH CE# Hold Time 1 µs TAS Address Setup Time 1 µs TAH Address Hold Time 1 µs TPRT VPP Pulse Rise Time 50 ns TVPS VPP Setup Time 1 µs TVPH VPP Hold Time 1 µs TPW PGM# Program Pulse Width 15 25 µs TEW PGM# Erase Pulse Width 100 200 ms TDS Data Setup Time 1 µs TDH Data Hold Time 1 µs TVR A9 Recovery Time for Erase 1 µs TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 µs TA9H A9 Hold Time during Erase 1 µs T10.0 1251 |
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