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SST37VF020-70-3C-PH Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc |
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SST37VF020-70-3C-PH Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc |
7 / 18 page Data Sheet 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 7 ©2006 Silicon Storage Technology, Inc. S71151-07-000 8/06 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters VDD = 2.7-3.6V (TA = 0°C to +70°C (Commercial)) Symbol Parameter SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70 Units Min Max TRC Read Cycle Time 70 ns TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns TCLZ1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. CE# Low to Active Output 0 ns TOLZ1 OE# Low to Active Output 0 ns TCHZ1 CE# High to High-Z Output 25 ns TOHZ1 OE# High to High-Z Output 25 ns TOH1 Output Hold from Address Change 0 ns T9.3 1151 TABLE 10: Program/Erase Cycle Timing Parameters VDD = 2.7-3.6V (TA = 25°C±5°C) Symbol Parameter Min Max Units TBP Byte-Program Time 20 µs TCES CE# Setup Time 1 µs TCEH CE# Hold Time 1 µs TAS Address Setup Time 1 µs TAH Address Hold Time 1 µs TDS Data Setup Time 1 µs TDH Data Hold Time 1 µs TPRT OE# Rise Time for Program and Erase 50 ns TVPS OE# Setup Time for Program and Erase 1 µs TVPH OE# Hold Time for Program and Erase 1 µs TPW WE# Program Pulse Width 15 25 µs TEW WE# Erase Pulse Width 100 200 ms TVR OE#/A9 Recovery Time for Erase 1 µs TART A9 Rise Time to 12V during Erase 50 ns TA9S A9 Setup Time during Erase 1 µs TA9H A9 Hold Time during Erase 1 µs T10.1 1151 |
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