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SST37VF010-70-3C-NH Datasheet(PDF) 1 Page - Silicon Storage Technology, Inc

Part # SST37VF010-70-3C-NH
Description  512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST37VF010-70-3C-NH Datasheet(HTML) 1 Page - Silicon Storage Technology, Inc

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©2006 Silicon Storage Technology, Inc.
S71151-07-000
8/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MTP is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)
Many-Time Programmable Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
FEATURES:
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8
2.7-3.6V Read Operation
Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
Low Power Consumption:
– Active Current: 10 mA (typical)
– Standby Current: 2 µA (typical)
Fast Read Access Time:
– 70 ns
Latched Address and Data
Fast Byte-Program Operation:
– Byte-Program Time: 15 µs (typical)
– Chip Program Time:
1 seconds (typical) for SST37VF512
2 seconds (typical) for SST37VF010
4 seconds (typical) for SST37VF020
8 seconds (typical) for SST37VF040
Electrical Erase Using Programmer
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
CMOS I/O Compatibility
JEDEC Standard Byte-wide Flash
EEPROM Pinouts
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
– Non-Pb (lead-free) packages available
PRODUCT DESCRIPTION
The SST37VF512/010/020/040 devices are 64K x8 / 128K
x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable
(MTP), low cost flash, manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST37VF512/010/020/040 can
be electrically erased and programmed at least 1000 times
using an external programmer, e.g., to change the contents
of devices in inventory. The SST37VF512/010/020/040
have to be erased prior to programming. These devices
conform to JEDEC standard pinouts for byte-wide flash
memories.
Featuring
high
performance
Byte-Program,
the
SST37VF512/010/020/040 provide a typical Byte-Pro-
gram time of 15 µs. Designed, manufactured, and tested
for a wide spectrum of applications, these devices are
offered with an endurance of at least 1000 cycles. Data
retention is rated at greater than 100 years.
The SST37VF512/010/020/040 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST37VF512/010/020/040 are offered in
32-lead PLCC, 32-lead TSOP, and 32-pin PDIP packages.
See Figures 2, 3, and 4 for pin assignments.
Device Operation
The SST37VF512/010/020/040 devices are nonvolatile
memory solutions that can be used instead of standard
flash devices if in-system programmability is not required. It
is functionally (Read) and pin compatible with industry
standard flash products.The device supports electrical
Erase operation via an external programmer.
Read
The Read operation of the SST37VF512/010/020/040 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (TCE). Data is available at the
output after a delay of TOE from the falling edge of OE#,
assuming the CE# pin has been low and the addresses
have been stable for at least TCE-TOE. When the CE# pin is
high, the chip is deselected and a standby current of only 2
µA (typical) is consumed. OE# is the output control and is
used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is VIH. Refer
to Figure 5 for the timing diagram.
SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories


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