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SST29EE512-70-4C-NHE Datasheet(PDF) 6 Page - Silicon Storage Technology, Inc |
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SST29EE512-70-4C-NHE Datasheet(HTML) 6 Page - Silicon Storage Technology, Inc |
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6 / 26 page  6 Data Sheet 512 Kbit Page-Write EEPROM SST29EE512 ©2005 Silicon Storage Technology, Inc. S71060-09-000 9/05 TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A15-A7 Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle. A6-A0 Column Address Inputs Column Addresses are toggled to load page data DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide: 5.0V supply (4.5-5.5V) for SST29EE512 VSS Ground NC No Connection Unconnected pins. T2.3 1060 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Page-Write VIL VIH VIL DIN AIN Standby VIH X1 1. X can be VIL or VIH, but no other value. X High Z X Write Inhibit X VIL X High Z/ DOUT X XX VIH High Z/ DOUT X Software Chip-Erase VIL VIH VIL DIN AIN, See Table 4 Product Identification Software Mode VIL VIH VIL Manufacturer’s ID (BFH) Device ID2 2. Device ID = 5DH for SST29EE512 See Table 4 SDP Enable Mode VIL VIH VIL See Table 4 SDP Disable Mode VIL VIH VIL See Table 4 T3.4 1060 |
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