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AK4529 Datasheet(PDF) 15 Page - Asahi Kasei Microsystems

Part No. AK4529
Description  High Performance Multi-channel Audio CODEC
Download  38 Pages
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK4529 Datasheet(HTML) 15 Page - Asahi Kasei Microsystems

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ASAHI KASEI
[AK4529]
MS0082-E-00
2001/3
- 15 -
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4529, are MCLK, LRCK and BICK. There are two methods to
set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS (Table 1). The
frequency of MCLK at each sampling speed is set automatically. (Table 2, 3). In Auto Setting Mode (ACKS = “1”), as
MCLK frequency is detected automatically (Table 4), and the internal master clock becomes the appropriate frequency
(Table 5), it is not necessary to set DFS.
MCLK should be synchronized with LRCK but the phase is not critical. External clocks (MCLK, BICK) should always be
present whenever the AK4529 is in normal operation mode (PDN = “H”). If these clocks are not provided, the AK4529
may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not
present, the AK4529 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting
reset at power-up etc., the AK4529 is in the power-down mode until MCLK and LRCK are input.
DFS
Sampling Speed (fs)
0
Normal Speed Mode
32kHz~48kHz
1
Double Speed Mode
64kHz~96kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK (MHz)
BICK (MHz)
fs
256fs
384fs
512fs
64fs
32.0kHz
8.1920
12.2880
16.3840
2.0480
44.1kHz
11.2896
16.9344
22.5792
2.8224
48.0kHz
12.2880
18.4320
24.5760
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
MCLK (MHz)
BICK (MHz)
fs
128fs
192fs
256fs
64fs
88.2kHz
11.2896
16.9344
22.5792
5.6448
96.0kHz
12.2880
18.4320
24.5760
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At double speed mode(DFS = “1”), 128fs and 192fs are not available for ADC.)
MCLK
Sampling Speed
512fs
Normal
256fs
Double
Table 4. Sampling Speed (Auto Setting Mode)


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