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AK4529 Datasheet(PDF) 6 Page - Asahi Kasei Microsystems |
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AK4529 Datasheet(HTML) 6 Page - Asahi Kasei Microsystems |
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6 / 38 page 
ASAHI KASEI [AK4529] MS0082-E-00 2001/3 - 6 - No. Pin Name I/O Function 23 LOUT3 O DAC3 Lch Analog Output Pin 24 ROUT3 O DAC3 Rch Analog Output Pin 25 LOUT2 O DAC2 Lch Analog Output Pin 26 ROUT2 O DAC2 Rch Analog Output Pin 27 LOUT1 O DAC1 Lch Analog Output Pin 28 ROUT1 O DAC1 Rch Analog Output Pin 29 NC - No Connect No internal bonding. 30 NC - No Connect No internal bonding. 31 LIN I Lch Analog Input Pin 32 RIN I Rch Analog Input Pin DZF2 O Zero Input Detect 2 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. 33 OVF O Analog Input Overflow Detect Pin (Note 3) This pin goes to “H” if the analog input of Lch or Rch is overflows. 34 VCOM O Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2µF is used to reduce power-supply noise. 35 VREFH I Positive Voltage Reference Input Pin, AVDD 36 AVDD - Analog Power Supply Pin, 4.5V ∼5.5V 37 AVSS - Analog Ground Pin, 0V 38 DZF1 O Zero Input Detect 1 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. 39 MCLK I Master Clock Input Pin 40 P/S I Parallel/Serial Select Pin “L”: Serial control mode, “H”: Parallel control mode DIF0 I Audio Data Interface Format 0 Pin in parallel control mode 41 CSN I Chip Select Pin in 3-wire serial control mode This pin should be connected to DVDD at I 2C bus control mode DIF1 I Audio Data Interface Format 1 Pin in parallel control mode 42 SCL/CCLK I Control Data Clock Pin in serial control mode I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I 2C Bus) LOOP0 I Loopback Mode 0 Pin in parallel control mode Enables digital loop-back from ADC to 4 DACs. 43 SDA/CDTI I/O Control Data Input Pin in serial control mode I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I 2C Bus) 44 TDM I TDM I/F Format Mode Pin (Note 1) “L”: Normal format, “H”: TDM format Notes: 1. SDOS, SMUTE, DFS, and TDM pins are ORed with register data if P/S = “L”. 2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All input pins should not be left floating. |
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