ASAHI KASEI

[AK93C85A/95A/10A]

DAM02E-03

2004/05

- 6 -

READ

The read instruction is the only instruction which outputs serial data on the DO pin.

Following the Start bit, first Op code and address are decoded, then the data from the selected

memory location is available at the DO pin.

A dummy bit (logical "0") precedes the 16-bit data from

the selected memory location.

The output data changes are synchronized with the rising edges of

the serial clock (SK).

The data in the next address can be read sequentially by continuing to provide clock.

The address

automatically cycles to the next higher address after the 16bit data shifted out.

AK93C85A・・When the highest address is reached ($3FF), the address counter rolls over

to address $000 allowing the read cycle to be continued indefinitely.

AK93C95A・・When the highest address is reached ($7FF), the address counter rolls over

to address $000 allowing the read cycle to be continued indefinitely.

AK93C10A・・When the highest address is reached ($FFF), the address counter rolls over

to address $000 allowing the read cycle to be continued indefinitely.

READ (AK93C85A)

READ (AK93C95A)

READ (AK93C10A)

17

16

address[A11–A0]+1

AK93C10A output a logic "1" (Ready status),

if previous instruction is WRITE.

Hi-Z

Hi-Z

Dummy

Bit

address[A11–A0]

0

CS

SK

DI

DO

Start bit

Op code

D0

12

34

5

14

15

D14

D15

A0

A1

A10

A11

0

1

1

0

31

32

46

47

D15

D1

D0

0

16

address[A10–A0]+1

AK93C95A output a logic "1" (Ready status),

if previous instruction is WRITE.

Hi-Z

Hi-Z

Dummy

Bit

address[A10–A0]

0

CS

SK

DI

DO

Start bit

Op code

D0

12

34

5

13

14

15

D14

D15

A0

A1

A9

A10

0

1

1

0

30

31

45

46

D15

D1

D0

0

address[A9–A0]+1

AK93C85A output a logic "1" (Ready status),

if previous instruction is WRITE.

Hi-Z

Hi-Z

Dummy

Bit

address[A9–A0]

0

CS

SK

DI

DO

Start bit

Op code

D0

1

2

3

4

5

12131415

D14

D15

A0

A1

A8

A9

0

1

1

0

29

30

44

45

D15

D1

D0

0