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AK8817 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems

Part No. AK8817
Description  NTSC/PAL Digital Video Encoder
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Maker  AKM [Asahi Kasei Microsystems]
Homepage  http://www.akm.com
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AK8817 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems

 
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ASAHI KASEI
[AK8817]
MS0413-E-03
4
2006 / 05
Pin Functional Description
Pin#
Pin Name
I/O
Functional Outline
G2
CLKIN
I
Clock input pin.
Input a clock which is synchronized with data.
When to input 601 data : 27 MHz.
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )
F1
CLKINV
I
Internal clock is inverted (internal operation timing edge is inverted.)
Connect to either PVDD or PVSS(DGND).
B5
PDN
I
Power Down Pin. After returning from PD mode to normal operation, RESET
Sequence should be done to AK8817.
“L “(GND level): Power-down
“H “: normal operation
A6
RSTN
I
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : normal operation
Hi-Z input is acceptable to this pin at PDN = L.
C7
SDA
I
I2C data pin.
This pin is pulled-up to PVDD.
Hi-Z input is possible when PDN is at low.
SDA input is not accepted during the reset sequence operation.
B6
SCL
I
I2C clock input pin
An input level of lower-than-PVDD should be input.
Hi-Z input is possible when PDN is at low.
SCL input is not accepted during the reset sequence operation.
F4
D7
I
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
G4
D6
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
F5
D5
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
G5
D4
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
F6
D3
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
G6
D2
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
F7
D1
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
E6
D0
I
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
C6
HDI
I
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
D7
VDI
I
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
C1
VREF
O
On-chip VREF output pin.
AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
C2
IREF
O
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor
( better than +/- 1% accuracy ).
A2
DACOUT
O
DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor
( better than +/- 1% accuracy ).
A4
VOUT
O
Video output pin.
A3
SAG
I/O
SAG Compensation Input pin
B1
AVDD
P
Analog power supply pin.
B2
AVSS
G
Analog ground pin.
A5, G3
DVDD
P
Digital power supply pin (digital core power supply).
B4, F3
DVSS
G
Digital ground pin (digital core ground).
E7
PVDD
P
Power supply pin for chip pad.
D6
PVSS
G
Ground pin for PVDD.
B3
BVSS
G
Substrate ground pin.
Connect this pin to Analog ground


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