1997 Apr 07

6

Philips Semiconductors

Preliminary specification

Digital Servo Driver 3 (DSD-3)

SZA1010

Fig.3 One of the digital drivers.

MBG786

M

(1)

VDD

VSS

TIMING

1-bit

code

clock

(1) Sledge motor; focus/radial motor.

Fig.4 1-bit code is logic 1.

MBG787

M

Ipos

(1)

VDD

VSS

TIMING

1-bit

code

'1'

clock

AB

CD

(1) Sledge motor; focus/radial motor.

Fig.5 1-bit code is logic 0.

MBG788

M

Ineg

(1)

VDD

VSS

TIMING

1-bit

code

'0'

clock

AB

CD

(1) Sledge motor; focus/radial motor.

Fig.6 Notch filter at input of digital drivers.

The filter consists of a simple delay element (flip-flop) and an adder.

MBG789

1-bit

1.5-bit

1/Z