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SSTL16877 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. SSTL16877
Description  14-bit SSTL_2 registered driver with differential clock inputs
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SSTL16877 Datasheet(HTML) 5 Page - NXP Semiconductors

   
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Philips Semiconductors
Product specification
SSTL16877
14-bit SSTL_2 registered driver with
differential clock inputs
2000 Apr 20
5
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0_C to +70_C (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 2.5 V ±0.2 V
UNIT
MIN
MAX
fclock
Clock frequency
200
MHz
tw
Pulse duration, CLK, CLK HIGH or LOW
1.0
ns
t
Setup time
Data before CLK
↑, CLK↓
0.2
ns
tsu
Setup time
RESET HIGH before CLK
↑, CLK↓
0.8
ns
th
Hold time
1.2
ns
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0_C to +70_C; VDDQ = 2.3 – 2.7 V and VDDQ does not exceed VCC.
Class I, VREF = VTT = VDDQ x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V ±0.2 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
fmax
Maximum clock frequency
200
MHz
tPLH/tPHL
CLK and CLK
Q
1.0
3.5
ns
tPHL
RESET
Q
2.0
4.0
ns
184/200-pin DDR SDRAM DIMM
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00502
CBT3867 (9)
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
SSTL16877
PCK877
SSTL16877
BACK SIDE
FRONT SIDE


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