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APPLICATION INFORMATION

Power-Sequencing Guidelines

TUSB6020

USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER

SCPS170C – JANUARY 2007 – REVISED JULY 2007

During powerup, the USB 2.0 OTG PHY macro is not suspended, and the 60-MHz system clock is enabled and

free running.

• The reference clock input is selected between CLKIN and XI based on the sense-on-reset.

• The default system clock is a device reference clock input (CLKIN or XI, depending on sampling GPIO6

during power-up).

• The digital core and PHY reset are synchronized to the system clock.

The Mentor Graphics MUSBMHDRC USB 2.0 dual-role controller powers up as a type-B device (B-Device bit in

the DevCtl register is set), and the OTG session is not enabled (session bit in the DevCtl register is set to 0).

With the session not started, all of the MUSBMHDRC finite state machines are in the idle state.

The TUSB6020 controller is in the normal state.

After the reset ID is deasserted, the device asserts the DevReady interrupt to the external host.

The external host responds to the interrupt. It reads the interrupt status register and decides how to proceed

based on the device’s current status.

confirm the USB cable connection.

• If no USB cable in attached, IDpullup should be high and V

• If the type-B USB connector is attached, IDpullup should be high. The V

• If the type-A USB connector is attached, IDpullup should be low and V

The external host may decide to place the device into idle state if:

• No USB cable is attached.

• The type-B connector is attached but the type-A device did not charge V

• The type-A connector is attached but the external host may decide to wait for an SRP request from the

type-B device.

The external host configures wake-up sources before setting the Idle bit. It does the following:

• Enables the IDpullup wake-up source

• Enables the V

• Enables the USB resume (LineState) wake-up source

• Enables the external host (NOR FLASH/VLYNQ) wake-up source

• Enables wake-up interrupts

The external host sets the Idle bit. The device starts the transition to the idle state. During transitions from the

normal to the idle state, the device ignores all wake-up events. The device can respond to wake-up events only

when in the idle state.

In the idle state, the device asserts the SLEEP output pin to the companion power-management device to place

it into low power/sleep mode if the PmIdle and DevIdle bits are set in the PRCM Power Management register. In

sleep state, the companion power-management device provides 100 A maximum per power rail (1.5 V and

3.3 V). The power-management device can be put into the sleep state only if the device is placed in the idle

state (DevIdle bit set).

If the application requires the companion power management device to remain in the normal state, the PmIdle

bit will not be set, while the DevIdle bit can be set to place the device into the idle state.

Figure 1 illustrates the power-up sequence.

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