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TSC2111 Datasheet(PDF) 48 Page - Texas Instruments |
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TSC2111 Datasheet(HTML) 48 Page - Texas Instruments |
48 / 99 page TSC2111 SLAS495− JUNE 2006 www.ti.com 48 A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. The idle state of the serial clock for the TSC2111 is low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The TSC2111 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the TSC2111 only interprets command words which are transmitted after the falling edge of SS. TSC2111 COMMUNICATION PROTOCOL Register Programming The TSC2111 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI master and accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in Figure 36. The command word begins with an R/W bit, which specifies the direction of data flow on the SPI serial bus. The following 4 bits specify the page of memory this command is directed to, as shown in Table 7. The next six bits specify the register address on that page of memory to which the data is directed. The last five bits are reserved for future use and should be written only with zeros. Table 7. Page Addressing PG3 PG2 PG1 PG0 PAGE ADDRESSED 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 1 0 0 0 Reserved 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved To read all the first page of memory, for example, the host processor must send the TSC2111 the command 0x8000 – this specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the TSC2111. The TSC2111 automatically increments its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the TSC2111 sends back the value 0xFFFF. Likewise, writing to page 1 of memory would consist of the processor writing the command 0x0800, which specifies a write operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointer pointing at the first location in memory on page 1. See the section on the TSC2111 memory map for details of register locations. BIT 15 MSB BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB R/W* PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0 0 0 0 0 |
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