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SCN68562C4A52 Datasheet(PDF) 5 Page - NXP Semiconductors |
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SCN68562C4A52 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 18 page Philips Semiconductors Product specification SCN68562 Dual universal serial communications controller (DUSCC) 1995 May 01 5 PIN DESCRIPTION In this data sheet, signals are discussed using the terms ‘active’ and ‘inactive’ or ‘asserted’ and ‘negated’ independent of whether the signal is active in the High (logic 1) or Low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is active-Low (see individual pin description for the definition of the active level of each signal.) Pins which are provided for both channels are designated by A/B after the name of the pin and the active-Low state indicator, N, if applicable. A similar method is used for registers provided for both channels: these are designated by either an underline or by A/B after the name. MNEMONIC DIP PIN NO. TYPE NAME AND FUNCTION A1 – A6 4-2, 45-47 I Address Lines: Active-High. Address inputs which specify which of the internal registers is accessed for read/write operation. D0 – D7 31-28, 21-18 I/O Bidirectional Data Bus: Active High, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data, command, and status transfers between the CPU and the DUSCC take place over this bus. The data bus is enabled when CSN is Low, during interrupt acknowledge cycles and single-address DMA acknowledge cycles. R/WN 26 I Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle when a cycle is initiated by assertion of the CSN input. CSN 25 I Chip Select: Active-Low input. When Low, data transfers between the CPU and the DUSCC are enabled on D0 – D7 as controlled by the R/WN and A1 – A6 inputs. When CSN is High, the DUSCC is isolated from the data bus (except during interrupt acknowledge cycles and single-address DMA transfers) and D0 – D7 are placed in the 3-State condition. DTACKN 22 O Data Transfer Acknowledge: Active-Low, 3-State. DTACKN is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. The signal is negated when completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to the inactive state (3-State) a short period after it is negated. In a single address DMA mode, data is latched with the falling edge of DTCN. DTACKN is negated when completion of the cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-State) a short period after it is negated. When negated, DTACKN becomes an open-drain output and requires an external pull-up resistor. IRQN 6 O Interrupt Request: Active-Low, open-drain. This output is asserted upon occurrence of any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the DUSCC to output an interrupt vector on the data bus. IACKN 1 I Interrupt Acknowledge: Active-Low. When IACKN is asserted, the DUSCC responds by placing the contents of the interrupt vector register (modified or unmodified by status) on the data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not asserted. X1/CLK 43 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins X1 and X2. If a crystal is not used, and external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. X2/IDCN 42 O Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is connected between pins X1 and X2. This pin can be programmed to provide and interrupt daisy chain active-Low output which propagates the IACKN signal to lower priority devices, if no active interrupt is pending. This pin should be grounded when an external clock is used on X1 and X2, is not used as an interrupt daisy chain output. RESETN 7 I Master Reset: Active-Low. A low on this pin resets the transmitters and receivers and resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset in asynchronous, i.e., no clock is required. RxDA, RxDB 37, 12 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. TxDA, TxDB 36, 13 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the marking (High) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. RTxCA, RTxCB 39, 10 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X). The maximum external receiver/transmitter clock frequency is 4MHz. |
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