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SCN68681 Datasheet(PDF) 23 Page - NXP Semiconductors |
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SCN68681 Datasheet(HTML) 23 Page - NXP Semiconductors |
23 / 28 page Philips Semiconductors Product specification SCN68681 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 23 TRANSMITTER ENABLED TxD ADD#1 TxRDY (SR2) CSN (WRITE) MR1(4+3) = 11 MR1(2) = 1 1 BIT 9 D0 0 BIT 9 ADD#2 1 BIT 9 MASTER STATION ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2 RxD ADD#1 1 BIT 9 D0 0 BIT 9 ADD#2 1 BIT 9 PERIPHERAL STATION 0 BIT 9 0 BIT 9 RECEIVER ENABLED RxRDY (SR0) CSN MR1(4:3) = 11 ADD#1 STATUS DATA D0 STATUS DATA ADD#2 SD00120 Figure 15. Wake-Up Mode Output Port Notes The output ports are controlled from three places: the OPCR register, the OPR register, and the MR registers. The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the “Set Output Port Bits Command”. These commands are at E and F, respectively. When these commands are used, action takes place only at the bit locations where ones exist. For example, a one in bit location 5 of the data word used with the “Set Output Port Bits” command will result in OPR5 being set to one. The OP5 would then be set to zero (VSS). Similarly, a one in bit position 5 of the data word associated with the “Reset Output Ports Bits” command would set OPR5 to zero, and hence, the pin OP5 to a one (VDD). The CTS, RTS, CTS Enable Tx signals CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin MPI. The CTS signal is active low; thus, it is called CTS. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active low and is, thus, called RTSN. RTSN is on pin MP0. A receiver’s RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2(4) is the bit that allows the transmitter to be controlled by the CTS pin (MPI). When this bit is set to one AND the CTS input is driven high, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter’s CTS input. The receiver will set RTS high when the receiver FIFO is full AND the start bit of the fourth character is sensed. Transmission then stops with four valid characters in the receiver. When MR2(4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2(4) is set to zero, the MP pin will have no effect on the operation of the transmitter. MR1(7) is the bit that allows the receiver to control MP0. When MP0 is controlled by the receiver, the meaning of that pin will be RTS. However, a point of confusion arises in that MP0 may also be controlled by the transmitter. When the transmitter is controlling this pin, its meaning is not RTS at all. It is, rather, that the transmitter has finished sending its last data byte. Programming the MP0 pin to be controlled by the receiver and the transmitter at the same time is allowed, but would usually be incompatible. RTS is expressed at the MP0 pin which is still an output port. Therefore, the state of MP0 should be set low for the receiver to generate the proper RTS signal. The logic at the output is basically a NAND of the MP0 bit register and the RTS signal as generated by the receiver. When the RTS flow control is selected via the MR(7) bit the state of the MP0 register is not changed. Terminating the use of “Flow Control” (via the MR registers) will return the MP0 pin to the control of the MP0 register. Transmitter Disable Note The sequence of instructions enable transmitter — load transmit holding register — disable transmitter will result in nothing being sent if the time between the end of loading the transmit holding register and the disable command is less that 3/16 bit time in the |
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