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SCN68681 Datasheet(PDF) 16 Page - NXP Semiconductors |
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SCN68681 Datasheet(HTML) 16 Page - NXP Semiconductors |
16 / 28 page Philips Semiconductors Product specification SCN68681 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 16 1: The Channel A receiver interrupt output which is the complement of ISR[1]. When in this mode OP4 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. OPCR[3:2] – OP3 Output Select This bit programs the OP3 output to provide one of the following: 00: The complement of OPR[3]. 01: The counter/timer output, in which case OP3 acts as an open- drain output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains High until terminal count is reached, at which time it goes Low. The output returns to the High state when the count- er is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR. 10: The 1X clock for the Channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. 11: The 1X clock for the Channel B receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. OPCR[1:0] – OP2 Output Select This field programs the OP2 output to provide one of the following: 00: The complement of OPR[2]. 01: The 16X clock for the Channel A transmitter. This is the clock selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] = 1111. 10: The 1X clock for the Channel A transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. 11: The 1X clock for the Channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. Table 4. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz NORMAL RATE (BAUD) ACTUAL 16x CLOCK (kHz) ERROR (%) 50 0.8 0 75 1.2 0 110 1.759 -0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 -0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 14.4K 230.4 0 19.2k 307.2 0 28.8K 460.8 0 38.4k 614.4 0 57.6K 921.6 0 115.2K 1843.2K 0 NOTE: Duty cycle of 16x clock is 50% ± 1%. Asynchronous UART communications can tolerate frequency error of 4.1% to 6.7% in a “clean” communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a stop bit length of 9/16 is used, the error tolerance will approach 0 due to a variable error of up to 1/16 bit time in receiver clock phase alignment to the start bit. Table 5. ACR 6:4 Field Definition ACR [6:4] MODE CLOCK SOURCE 000 Counter External (IP2)* 001 Counter TxCA – 1x clock of Channel A transmitter 010 Counter TxCB – 1x clock of Channel B transmitter 011 Counter Crystal or external clock (x1/CLK) divided by 16 100 Timer (square wave) External (IP2)* 101 Timer (square wave) External (IP2) divided by 16* 110 Timer (square wave) Crystal or external clock (X1/CLK) 111 Timer (square wave) Crystal or external clock (X1/CLK) divided by 16 NOTE: * In these modes, the Channel B receiver clock should normally be generated from the baud rate generator. Timer mode generates squarewave. ACR – Auxiliary Control Register ACR[7] – Baud Rate Generator Set Select This bit selects one of two sets of baud rates to be generated by the BRG: Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, and 38.4k baud. Set 2: 75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, 9.6k, and 19.2k baud. The selected set of rates is available for use by the Channel A and B receivers and transmitters as described in CSRA and CSRB. Baud rate generator characteristics are given in Table 4. ACR[6:4] – Counter/Timer Mode And Clock Source Select This field selects the operating mode of the counter/timer and its clock source as shown in Table 5. ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR[7]) to be set. If a bit is in the ‘on’ state the setting of the corresponding bit in the IPCR will also result in the setting of ISR[7], which results in the generation of an interrupt output if IMR[7] = 1. If a bit is in the ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7]. IPCR – Input Port Change Register IPCR[7] – IP3, IP2, IP1, IP0 Change-of-State These bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. |
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