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SCN68681 Datasheet(PDF) 10 Page - NXP Semiconductors

Part # SCN68681
Description  Dual asynchronous receiver/transmitter DUART
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SCN68681 Datasheet(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
SCN68681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
10
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in
the receiver, by connecting the RTSN output to the CTSN input of
the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver after
a disable will cause the receiver to begin assembling characters at the
next start bit detected. A receiver reset will discard the present shift
register data, reset the receiver ready bit (RxRDY), clear the status of
the byte at the top of the FIFO and re-align the FIFO read/write
pointers. This has the appearance of “clearing or flushing” the
receiver FIFO. In fact, the FIFO is NEVER cleared! The data in the
FIFO remains valid until overwritten by another received character.
Because of this, erroneous reading or extra reads of the receiver
FIFO will miss-align the FIFO pointers and result in the reading of
previously read data. A receiver reset will re-align the pointers.
Multidrop Mode
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3] or
MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of
operation, a ‘master’ station transmits an address character followed by
data characters for the addressed ‘slave’ station. The slave stations,
with receivers that are normally disabled, examine the received data
stream and ‘wake up’ the CPU (by setting RxRDY) only upon receipt of
an address character. The CPU compares the received address to its
station address and enables the receiver if it wishes to receive the
subsequent data characters. Upon receipt of another address character,
the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted
A/D bit is selected by the CPU by programming bit
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
which identifies the corresponding data bits as an address. The
CPU should program the mode register prior to loading the
corresponding data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by RESET
or by issuing a ‘reset pointer’ command via the corresponding
command register. Any read or write of the mode register while the
pointer is at MR1x, switches the pointer to MR2x. The pointer then
remains at MR2x, so that subsequent accesses are always to MR2x
unless the pointer is reset to MR1x as described above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The reserved
registers at addresses H‘02’ and H‘OA’ should never be read during
normal operation since they are reserved for internal diagnostics.
Table 1.
SCN68681 Register Addressing
A4
A3
A2
A1
READ (R/WN = 1)
WRITE (R/WN = 0)
0
0
0
0
Mode Register A (MR1A, MR2A)
Mode Register A (MR1A, MR2A)
0
0
0
1
Status Register A (SRA)
Clock Select Register A (CSRA)
0
0
1
0
BRG Test
Command Register A (CRA)
0
0
1
1
Rx Holding Register A (RHRA)
Tx Holding Register A (THRA)
0
1
0
0
Input Port Change Register (IPCR)
Aux. Control Register (ACR)
0
1
0
1
Interrupt Status Register (ISR)
Interrupt Mask Register (IMR)
0
1
1
0
Counter/Timer Upper Value (CTU)
C/T Upper Preset Value (CRUR)
0
1
1
1
Counter/Timer Lower Value (CTL)
C/T Lower Preset Value (CTLR)
1
0
0
0
Mode Register B (MR1B, MR2B)
Mode Register B (MR1B, MR2B)
1
0
0
1
Status Register B (SRB)
Clock Select Register B (CSRB)
1
0
1
0
1X/16X Test
Command Register B (CRB)
1
0
1
1
Rx Holding Register B (RHRB)
Tx Holding Register B (THRB)
1
1
0
0
Interrupt Vector Register (IVR)
Interrupt Vector Register (IVR)
1
1
0
1
Input Ports IP0 to IP6
Output Port Conf. Register (OPCR)
1
1
1
0
Start Counter Command
Set Output Port Bits Command
1
1
1
1
Stop Counter Command
Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication


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