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SCN68681 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. SCN68681
Description  Dual asynchronous receiver/transmitter DUART
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SCN68681 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
SCN68681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
5
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
D0-D7
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
CSN
I
Chip Select: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on
D0-D7 as controlled by the R/WN, RDN and A1-A4 inputs. When High, places the D0-D7 lines in the 3-State condition.
R/WN
I
Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle, when a cycle is initiated by
assertion of the CSN input.
A1-A4
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESETN
I
Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts
OP0-OP7 in the High state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MR1.
DTACKN
O
Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate
proper transfer of data between the CPU and the DUART.
INTRN
O
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
IACKN
I
Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the DUART will
place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
X1/CLK
I
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
X2
I
Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although
it is permissible to ground it.
RxDA
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
RxDB
I
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
TxDA
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
“mark” condition when the transmitter is disabled, idle or when operating in local loopback mode. “Mark” is High,
“space” is Low.
TxDB
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is High,
‘space’ is Low.
OP0
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated
automatically on receive or transmit.
OP1
O
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated
automatically on receive or transmit.
OP2
O
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock
output.
OP3
O
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock
output, or Channel B receiver 1X clock output.
OP4
O
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output.
OP5
O
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output.
OP6
O
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7
O
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYB output.
IP0
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal VCC
pull-up device supplying 1 to 4
mA of current.
IP1
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal VCC
pull-up device supplying 1 to 4
mA of current.
IP2
I
Input 2: General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock
input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
IP3
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4
mA of current.
IP4
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used
by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4
mA of current.
IP5
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4
mA of current.
VCC
I
Power Supply: +5V supply input.
GND
I
Ground:


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