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MH64D72KLH-75 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part No. MH64D72KLH-75
Description  4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH64D72KLH-75 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor

 
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0390-1.0
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
1
DESCRIPTION
APPLICATION
Main memoryunit for PC, PC server, Server, W S.
FEATURES
Type name
133MHz
MH64D72KLH-10
MH64D72KLH-75
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
-
Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cyc le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Diff erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cyc les /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
Max.
Frequency
100MHz
1pin
52pin
92pin
93pin
144pin
145pin
184pin
The MH64D72KLH is 67108864 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 18 industry standard 32M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
53pin
+ 0.75ns
+ 0.8ns


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