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SCN2681 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. SCN2681
Description  Dual asynchronous receiver/transmitter DUART
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SCN2681 Datasheet(HTML) 6 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
6
AC CHARACTERISTICS TA = -40°C to +85°C1, VCC = +5.0V " 10%2, 3, 4, 5
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Typ
Max
UNIT
Reset Timing (Figure 3)
tRES
RESET pulse width
200
ns
Bus Timing (Figure 4)6
tAS
A0-A3 setup time to RDN, WRN Low
10
ns
tAH
A0-A3 hold time from RDN, WRN Low
100
ns
tCS
CEN setup time to RDN, WRN Low
0
ns
tCH
CEN hold time from RDN, WRN High
0
ns
tRW
WRN, RDN pulse width
225
ns
tDD
Data valid after RDN Low
175
ns
tDF
Data bus floating after RDN High
100
ns
tDS
Data setup time before WRN High
100
ns
tDH
Data hold time after WRN High
20
ns
tRWD
High time between READs and/or WRITE7, 8
200
ns
Port Timing (Figure 5)6
tPS
Port input setup time before RDN Low
0
ns
tPH
Port input hold time after RDN High
0
ns
tPD
Port output valid after WRN High
400
ns
Interrupt Timing (Figure 6)
tIR
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
300
ns
Write THR (TxRDY interrupt)
300
ns
Reset command (delta break interrupt)
300
ns
Stop C/T command (counter interrupt)
300
ns
Read IPCR (input port change interrupt)
300
ns
Write IMR (clear of interrupt mask bit)
300
ns
Clock Timing (Figure 7)10
tCLK
X1/CLK High or Low time
100
ns
fCLK
X1/CLK frequency
2.0
3.6864
4.0
MHz
tCTC
CTCLK (IP2) High or Low time
100
ns
fCTC
CTCLK (IP2) frequency
0
4.0
MHz
tRX9
RxC High or Low time
220
ns
fRX9
RxC frequency (16X)
(1X)
0
0
2.0
1.0
MHz
MHz
tTX9
TxC High or Low time
220
ns
fTX9
TxC frequency (16X)
(1X)
0
0
2.0
1.0
MHz
MHz
Transmitter Timing (Figure 8)
tTXD9
TxD output delay from TxC external clock input on IP pin
350
ns
tTCS9
Output delay from TxC low at OP pin to TxD data output
0
150
ns
Receiver Timing (Figure 10)
tRXS9
RxD data setup time before RxC high at external clock input on IP pin
240
ns
tRXH9
RxD data hold time after RxC high at external clock input on IP pin
200
ns
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150
°C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of < 20ns. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V
and 2.0V as appropriate.
4. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: CL = 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
9. This parameter is not applicable to the 28-pin device.
10. Operation to 0MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.


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