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SC28L198A1 Datasheet(PDF) 32 Page - NXP Semiconductors |
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SC28L198A1 Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 56 page  Philips Semiconductors Product specification SC28L198 Octal UART for 3.3V and 5V supply voltage 1999 Jan 14 32 Table 44. Summary Register Map, Data Address (hex) ccc = Channel Register Name Acronym Read/Write 1ccc 0000 (x80) Mode Register 2 MR2 R/W 1ccc 0001 (x81) Status Register SR R 1ccc 0001 (x81) Command Register CR W 1ccc 0010 (x82) Interrupt Status Register ISR R 1ccc 0010 (x82) Interrupt Mask Register IMR W 1ccc 0011 (x83) Transmitter FIFO Register TxFIFO W 1ccc 0011 (x83) Receiver FIFO Reg RxFIFO R 1ccc 0100 (x84) Input Port Reg IPR R 1000 0100 (x84) ♣ BRG Timer Reg Upper a BRGTRUa W 1ccc 0101 (x85) I/O Port Interrupt and Output I/OPIOR R/W 1ccc 0110 (x86) Xon/Xoff Interrupt Status Reg XISR R 1000 0111 (x87) ♣ GP Out Select Reg GPOSR R/W 1000 1011 (x8B) ♣ GP Out Clk Reg GPOC R/W 1000 1100 (x8C) ♣ Update Current Interrupt Reg UCIR W 1000 1100 (x8C) ♣ Current Interrupt Reg CIR R 1001 1101 (x9D) ♣ BRG Timer Reg Upper b BRGTRUb W 1000 1110 (x8E) ♣ Global Receive FIFO Reg GRxFIFO R 1000 1110 (x8E) ♣ Global Transmit FIFO Reg GTxFIFO W 1000 1111 (x8F) ♣ Global Chip Configuration Reg GCCR R/W 1001 0100 (x94) ♣ BRG Timer Reg Lower a BGRTRLa W 1001 0111 (x97) ♣ GP Output Reg GPOR R/W 1001 1011 (x9B) ♣ GP Out Data Reg GPOD R/W 1001 1100 (x9C) ♣ BRG Timer Control Reg BRGTCR W 1001 1100 (x9C) ♣ Global Interrupt Channel Reg GICR R 1001 1101 (x9D) ♣ BRG Timer Reg Lower b BRGTRLb W 1001 1101 (x9D) ♣ Global Interrupt Byte Count GIBCR R 1001 1111 (x9F) ♣ Global Interrupt Type Register GITR R REGISTER MAP DETAIL Table 45. Register Map, Control NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a ♣ symbol A(7:0) UART A A(7:0) Read Write 0000 0000 (x00) Mode Register 0 MR0a Mode Register 0 MR0a 0000 0001 (x01) Mode Register 1 MR1a Mode Register 1 MR1a 0000 0010 (x02) I/O Port Configuration Reg a I/OPCRa I/O Port Configuration Reg a I/OPCRa 0000 0011 (x03) BCRBRKa BCRBRKa 0000 0100 (x04) BCRCOSa BCRCOSa 0000 0101 (x05) Reserved Reserved 0000 0110 (x06) BCRXa BCRXa 0000 0111 (x07) BCRAa BCRAa 0000 1000 (x08) Xon Character Reg a (XonCRa) Xon Character Reg a (XonCRa) 0000 1001 (x09) Xoff Character Reg a (XoffCRa) Xoff Character Reg a (XoffCRa) 0000 1010 (x0A) Address Recognition Character a (ARCRa) Address Recognition Character a (ARCRa) 0000 1011 (x0B) Reserved Reserved 0000 1100 (x0C) Receiver Clock Select Register a (RxCSRa) Receiver Clock Select Register a (RxCSRa) 0000 1101 (x0D) ♣ Test Register Test Register 0000 1110 (x0E) Xmit Clock Select Register a TxCSRa) Xmit Clock Select Register a TxCSRa) 0000 1111 (x0F) ♣ Global Chip Configuration Reg(GCCR) Global Chip Configuration Reg GCCR) |
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