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SC28L198A1 Datasheet(PDF) 17 Page - NXP Semiconductors |
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SC28L198A1 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 56 page  Philips Semiconductors Product specification SC28L198 Octal UART for 3.3V and 5V supply voltage 1999 Jan 14 17 activity of the Xon/Xoff logic is initiated by commands to the CRx command forces the transmitter to disable exactly as though an Xoff character had been received by the RxFIFO. The transmitter will remain disabled until the chip is reset or the CR(7:3) = 10110 (Xoff resume) command is given. In particular, reception of an Xon or disabling or re–enabling the transmitter will NOT cause resumption of transmission. Redundant CRTXon/off commands, i.e. CRTXon CRTXon, are harmless, although they waste time. A CRTXon may be used to cancel a CRTXoff (and vice versa), but both may be transmitted depending on the timing with the transmit state machine. The kill CRTX command can be used to cleanly terminate any CRTX commands pending with the minimum impact on the transmitter. Note: In no case will an Xon/Xoff character transmission be aborted. Once the character is loaded into the TX Shift Register, transmission continues until completion or a chip reset is encountered. The kill CRTX command has no effect in either of the Auto modes. Mode control Xon/Xoff mode control is accomplished via the MR0. Bits 3 and 2 reset to zero resulting in all Xon/Xoff processing being disabled. If MR0[2] is set, the transmitter may be gated by Xon/Xoff characters received. If MR0[3] is set, the transmitter will transmit Xon and Xoff when triggered by attainment of fixed fill levels in the channel RxFIFO. The MR0[7] bit also has an Xon/Xoff function control. If this bit is set, a received Xon or Xoff character is not pushed into the RxFIFO. If cleared, the power–on and reset default, the received Xon or Xoff character is pushed onto the RxFIFO for examination by the host CPU. The MR0(7) function operates regardless of the value in MR0(3:2) Xon/Xoff Interrupts The Xon/Xoff logic generates interrupts only in response to recognizing either of the characters in the XonCR or XoffCR (Xon or Xoff Character Registers). The transmitter activity initiated by the Xon/Xoff logic or any CR command does not generate an interrupt. The character comparators operate regardless of the value in MR0(3:2). Hence the comparators may be used as general purpose character detectors by setting MR0(3:2)=’00’ and enabling the Xon/Xoff interrupt in the IMR. The Octal UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid level of an Xon/Xoff recognition event is controlled by the Bidding Control Register X, BCRX, of the channel. The interrupt status can be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is interrupting. If set, an Xon or Xoff recognition event has been detected. The X Interrupt Status Register, XISR, can be read for details of the interrupt and to examine other, non–interrupting, status of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions. The character recognition function and the associated interrupt generation is disabled on hardware or software reset . |
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