Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

21

asserted (low), the character is transmitted. If it is negated (high),

the TxD output remains in the marking state and the transmission is

delayed until CTSN goes low. Changes in CTSN, while a character

is being transmitted, do not affect the transmission of that character.

This feature can be used to prevent overrun of a remote receiver.

MR2[3:2] – RxINT control field

Controls when interrupt arbitration for a receiver begins based on

RxFIFO fill level. This field allows interrupt arbitration to begin when

the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1

character.

MR2[1:0] – Stop Bit Length Select

This field programs the length of the stop bit appended to the

transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can

be programmed for character lengths of 6, 7, and 8 bits. For a

character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.

In all cases, the receiver only checks for a mark condition at the

center of the first stop bit position (one bit time after the last data bit,

or after the parity bit if parity is enabled). If an external 1X clock is

used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]

= 1 selects two stop bits to be transmitted.

Table 6. RxCSR and TxCSR – Receiver and Transmitter Clock Select Registers

Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this

register read b’111. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown

below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.

Bits 7:5

Bits 4:0

Reserved

Transmitter/Receiver Clock select code, (see Clock Mux Table below)

Table 7. Data Clock Mux

CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.

Clock Select Code

CSR (4:0)

Clock selection,

CCLK = 3.6864 MHz

Clock Select Code

Clock selection,

CCLK = 3.6864 MHz

00000

BRG – 50

10000

BRG – 19.2K

00001

BRG – 75

10001

BRG – 28.8K

00010

BRG – 150

10010

BRG – 38.4K

00011

BRG – 200

10011

BRG – 57.6K

00100

BRG – 300

10100

BRG – 115.2K

00101

BRG – 450

10101

BRG – 230.4K

00110

BRG – 600

10110

00111

BRG – 900

10111

01000

BRG – 1200

11000

BRG C/T 0

01001

BRG – 1800

11001

BRG C/T 1

01010

BRG – 2400

11010

Reserved

01011

BRG – 3600

11011

I/O2 rcvr, I/O3 xmit –16x

01100

BRG – 4800

11100

I/O2 rcvr, I/O3 xmit–1x

01101

BRG – 7200

11101

Reserved

01110

BRG – 9600

11110

Reserved

01111

BRG – 14.4K

11111

Reserved