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SC28L194A1A Datasheet(PDF) 5 Page - NXP Semiconductors |
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SC28L194A1A Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 52 page Philips Semiconductors Preliminary specification SC28L194 Quad UART for 3.3V and 5V supply voltage 1998 Sep 21 5 BLOCK DIAGRAM Block Diagram SC28L194 FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL FULL DUPLEX UART CHANNEL INPUT BUFFERS AND OUTPUT DRIVERS SD00524 Figure 2. Block Diagram As shown in the block diagram, the Quad UART consists of an interrupt arbiter, host interface, timing blocks and four UART channel blocks. The four channels blocks operate independently, interacting only with the timing, host I/F and interrupt blocks. FUNCTIONAL DESCRIPTION The SC28L194 is composed of several functional blocks: • Synchronous host interface block • A timing block consisting of a common baud rate generator making 22 industry standard baud rates and 2 16-bit counters used for non-standard baud rate generation • 4 identical independent full duplex UART channel blocks • Interrupt arbitration system evaluating 24 contenders • I/O port control section and change of state detectors. CONCEPTUAL OVERVIEW Host Interface The Host interface is comprised of the signal pins CEN, W/RN, IACKN, DACKN, IRQN Sclk and provides all the control for data transfer between the external and internal data buses of the host and the QUART. The host interface operates in a synchronous mode with the system (Sclk) which has been designed for a nominal operating frequency of 33 MHz. The interface operates in either of two modes; synchronous or asynchronous to the Sclk However the bus cycle within the QUART always takes place in four Sclk cycles after CEN is recognized. These four cycles are the C1, C2, C3, C4 periods shown in the timing diagrams. DACKN always occurs in the C4 time and occurs approximately 18 ns after the rising edge of C4. Addressing of the various functions of the QUART is through the address bus A(7:0). To maintain upward compatibility with the SC28L/C198 Octart the 8 bit address is still defined as such. However A(6) is NOT used and is internally connected to Vss (ground). The pin is, therefore, not included in the pin diagram. The address space is controlled by A(5:0) and A(7). A[7], in a general sense, is used to separate the data portion of the circuit from the control portion. Asynchronous bus cycle The asynchronous mode requires one bus cycle of the chip select (CEN) for each read or write to the chip. No more action will occur on the bus after the C4 time until CEN is returned high. Synchronous bus cycle In the synchronous mode a read or write will be done every four cycles of the Sclk. CEN does not require cycling but must remain low to keep the synchronous accesses active. This provides a burst mode of access to the chip. In both cases each read or write operation(s) will be completed in four (4) Sclk cycles. The difference in the two modes is only that the asynchronous mode will not begin another bus cycle if the CEN remains active after the four internal Sclk have completed. Internally the asynchronous cycle will terminate after the four periods of Sclk regardless of how long CEN is held active In all cases the internal action will terminate at the withdrawal of CEN. Synchronous CEN cycles shorter than multiples of four Sclk cycles minus 1 Sclk and asynchronous CEN cycles shorter than four Sclk cycles may cause short read or write cycles and produce corrupted data transfers. Timing Circuits The timing block consists of a crystal oscillator, a fixed baud rate generator (BRG), a pair of programmable 16 bit register based counters. A buffer for the System Clock generates internal timing for processes not directly concerned with serial data flow. Crystal Oscillator The crystal oscillator operates directly from a crystal, tuned between 1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with a minimum of external components. BRG values listed for the clock select registers correspond to a 3.6864 MHz crystal frequency. Use of a 7.3728 MHz crystal will double the Communication Clock frequencies. An external clock in the 100 KHz to 10 MHz frequency range may be connected to X1/CCLK. If an external clock is used instead of a crystal, X1/CCLK must be driven and X2 left floating. The X1 clock serves as the basic timing reference for the baud rate generator (BRG) and is available to the BRG timers. The X1 oscillator input |
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