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SAB9083H Datasheet(PDF) 5 Page - NXP Semiconductors |
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SAB9083H Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 24 page  1999 Nov 12 5 Philips Semiconductors Preliminary specification Multistandard Picture-In-Picture (PIP) controller SAB9083 n.c. 52 to 60 − not connected VSSD(RP) 61 S digital ground for memory periphery VSSD(T8) and VSSD(T9) 62 and 63 S digital ground for test VDDD(P2) 64 S digital supply voltage for periphery VSSD(P2) 65 S digital ground for periphery VSSD(D) 66 S digital ground for digital core VDDD(D) 67 S digital supply voltage for digital core FBL 68 O fast blanking control signal output (CMOS levels; +5 V tolerant) PKOFF 69 O peak off control signal output (CMOS levels; +5 V tolerant) DVSYNC 70 I vertical sync display channel input (CMOS levels; +5 V tolerant) DCLK 71 I test clock input (28 MHz; CMOS levels) SVSYNC 72 I vertical sync for subchannel input (CMOS levels; +5 V tolerant) SCL 73 I/O input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant) SDA 74 I/O input/output serial data/acknowledge output (I2C-bus; +5 V tolerant) POR 75 I power-on reset input (CMOS levels; pull-up resistor connected to VDD) VDDA(SA) 76 S analog supply voltage for subchannel ADCs VSSA(SA) 77 S analog ground for subchannel ADCs VDDA(SF) 78 S analog supply voltage for subchannel front-end buffers and clamps SU 79 I analog U input for subchannel Vref(B)(SA) 80 I/O input/output analog bottom reference voltage for subchannel ADCs SV 81 I analog V input for subchannel Vref(T)(SA) 82 I/O input/output analog top reference voltage for subchannel ADCs SY 83 I analog Y input for subchannel Vbias(SA) 84 I/O analog bias reference voltage for subchannel ADCs VSSD(SA) 85 S digital ground for subchannel ADCs VDDD(SA) 86 S digital supply voltage for subchannel ADCs SHSYNC 87 I horizontal sync input for subchannel (Vi <VSHSYNC) T6 88 I/O test data input/output bit 7 (CMOS levels) VDDA(SP) 89 S analog supply voltage for subchannel PLL VSSA(SP) 90 S analog ground for subchannel PLL VSSA(DP) 91 S analog ground for display channel PLL VDDA(DP) 92 S analog supply voltage for display channel PLL T7 93 I/O test data input/output bit 6 (CMOS levels) DHSYNC 94 I horizontal sync input for display channel (Vi <VDHSYNC) VDDD(MA) 95 S digital supply voltage for main channel ADCs VSSD(MA) 96 S digital ground for main channel ADCs Vbias(MA) 97 I/O analog bias reference voltage for main channel ADCs MY 98 I analog Y input for main channel Vref(T)(MA) 99 I/O analog top reference voltage for main channel ADCs MV 100 I analog V input for main channel SYMBOL PIN TYPE DESCRIPTION |
Similar Part No. - SAB9083H |
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Similar Description - SAB9083H |
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