Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MACH220-10 Datasheet(PDF) 15 Page - Advanced Micro Devices

Part No. MACH220-10
Description  High-Density EE CMOS Programmable Logic
Download  33 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
Logo 

MACH220-10 Datasheet(HTML) 15 Page - Advanced Micro Devices

Zoom Inzoom in Zoom Outzoom out
 15 / 33 page
background image
AMD
15
MACH220-14/18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25
°C,
6
pF
COUT
Output Capacitance
VOUT= 2.0 V
f = 1 MHz
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-14
-24
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
14.5
18
24
ns
8.5
12
16
ns
10
13.5
17
ns
tH
Register Data Hold Time
0
0
0
ns
tCO
Clock to Output (Note 3)
10
12
14.5
ns
tWL
7.5
7.5
10
ns
tWH
7.5
7.5
10
ns
53
40
32
MHz
50
38
30.5
MHz
fMAX
61.5
53
38
MHz
57
44
34.5
MHz
66.5
66.5
50
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
8.5
12
16
ns
tHL
Latch Data Hold Time
0
0
0
ns
tGO
Gate to Output (Note 3)
12
13.5
14.5
ns
tGWL
Gate Width LOW
7.5
7.5
10
ns
tPDL
Input, I/O, or Feedback to Output Through Transparent
17
20.5
26.5
ns
Input or Output Latch
tSIR
Input Register Setup Time
2.5
2.5
2.5
ns
tHIR
Input Register Hold Time
3
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
18
22
28
ns
tICS
Input Register Clock to Output Register Setup
14.5
18
24
ns
16
19.5
25.5
ns
tWICL
7.5
7.5
10
ns
tWICH
7.5
7.5
10
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL+ tWICH)
66.5
66.5
50
MHz
tSIL
Input Latch Setup Time
2.5
2.5
2.5
ns
tHIL
Input Latch Hold Time
3
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
20.5
24
30
ns
tIGOL
Input Latch Gate to Output Through Transparent
23
26.5
32.5
ns
Output Latch
tSLL
Setup Time from Input, I/O, or Feedback Through
11
14.5
18
ns
Transparent Input Latch to Output Latch Gate
tIGS
Input Latch Gate to Output Latch Setup
16
19.5
25.5
ns
tWIGL
Input Latch Gate Width LOW
7.5
7.5
10
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
19.5
23
29
ns
Input and Output Latches
-18
Maximum
Frequency
(Note 1)
tS
Setup Time from Input, I/O, or Feedback to Clock
1/(tS + tCO)
Internal Feedback (fCNT)
No Feedback
1/(tWL + tWH)
External Feedback
Clock Width
D-type
T-type
D-type
T-type
D-type
T-type
D-type
T-type
LOW
HIGH
LOW
HIGH
Input Register Clock Width


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn