Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

SAA8122A Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. SAA8122A
Description  Digital Still Camera Processor ImagIC family
Download  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA8122A Datasheet(HTML) 1 Page - NXP Semiconductors

  SAA8122A Datasheet HTML 1Page - NXP Semiconductors SAA8122A Datasheet HTML 2Page - NXP Semiconductors SAA8122A Datasheet HTML 3Page - NXP Semiconductors SAA8122A Datasheet HTML 4Page - NXP Semiconductors SAA8122A Datasheet HTML 5Page - NXP Semiconductors SAA8122A Datasheet HTML 6Page - NXP Semiconductors SAA8122A Datasheet HTML 7Page - NXP Semiconductors SAA8122A Datasheet HTML 8Page - NXP Semiconductors SAA8122A Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 26 page
background image
Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective specification
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,
which is dedicated to image processing, compression, formatting and storage. The
DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,
2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy
implementation of a complete system solution and fast development of high
performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments
and connections required for a wide range of Digital Still Cameras. Its embedded
RISC CPU, for which the development environment is available, enables shorter
development and validation cycles, as well as faster feature upgrade. Since one of
the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a
DSP (with advanced embedded algorithm) for camera signal processing is integrated
with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data
2.1 General
s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),
with RGB Bayer filters up to 2 Mpixels
s Performs an advanced RGB to YUV conversion
s Includes a smart measurement unit to speed up the control loop (focus, auto white
balance, etc.)
s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text
insertion features
s Includes an embedded JPEG encoder/decoder unit
s Includes a MIPS PR3001 CPU, running at a frequency in a range from
12 to 28 MHz
s PRISC compatible PI-bus architecture, interrupt, power management, clock and
reset architectures
s Includes a dedicated video bus supporting SDRAM memory for picture storage

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26 

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn