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SAA7391 Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA7391 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 108 page 1997 Aug 01 8 Philips Semiconductors Objective specification ATAPI CD-R block encoder/decoder SAA7391 n.c. 71 to 74 −− − not connected DD11 75 I/O AL/T host data bus; pin order of ATAPI interface matches the pinning of the 40-way IDE connector (slew rate limiting by control of drive capability into capacitive load of ATA bus) DD3 76 I/O AL/T DD12 77 I/O AL/T DD2 78 I/O AL/T DD13 79 I/O AL/T DD1 80 I/O AL/T DD14 81 I/O AL/T DD0 82 I/O AL/T DD15 83 I/O AL/T DMARQ/ DMACK 84 O AL host DMA request/SCSI DMA acknowledge output (active LOW) DGND7 85 −− − digital ground 7 VDDD(pad2) 86 −− − digital peripheral supply voltage 2 DIOW 87 I L/T host write cycle write enable/control register write input (active LOW) DIOR 88 I L/T host read cycle read enable/control register read input (active LOW) IORDY 89 O AH host device is ready to transfer data output (active LOW) DMACK/ DMARQ 90 I T host DMA acknowledge (active LOW)/SCSI DMA request input INTRQ 91 A host host interrupt request (NB 3-state output) DGND8 92 −− − digital ground 8 VDDD(pad3) 93 −− − digital peripheral supply voltage 3 IOCS16 94 O AH host I/O port is 16-bit output (active LOW) DA1/DBWR 95 I/O L/T host address wire 1/DMA from generic interface is output from the SAA7391 (active LOW) PDIAG 96 I/O AL/T host ATAPI passed diagnostics input/output (active LOW) DA0 97 I/O L/T host address wire 0 input/output DA2/DBRD 98 I/O L/T host address wire 2/DMA from generic interface is input to the SAA7391 (active LOW) CS0/ SCSICS 99 I/O L/T host chip select 1FX/generic interface chip select (active LOW) CS1 100 I/O L/T host chip select 3FX input/output (active LOW) DASP 101 I/O AH/T host device active slave present input/output (active LOW) INT2 102 O L sub-CPU sub-CPU interrupt output from the SAA7391 drive block and UART SYMBOL PIN TYPE DRIVE/ THRESHOLD GROUPING DESCRIPTION |
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