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SAA7388 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. SAA7388
Description  Error correction and host interface IC for CD-ROM ELM
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7388 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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1996 Apr 26
5
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
6
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
DGND1
1
digital ground 1
RA6
2
O
buffer RAM address bus output line 6
RA7
3
O
buffer RAM address bus output line 7
RA8
4
O
buffer RAM address bus output line 8
RA9
5
O
buffer RAM address bus output line 9
RA10
6
O
buffer RAM address bus output line 10
RA11
7
O
buffer RAM address bus output line 11 (SRAM) only
RA12
8
O
buffer RAM address bus output line 12 (SRAM) only
RA13
9
O
buffer RAM address bus output line 13 (SRAM) only
RA14
10
O
buffer RAM address bus output line 14 (SRAM) only
RA15/RAS
11
O
buffer RAM address bus output line 15 (SRAM) or RAS (DRAM)
RA16/CAS
12
O
buffer RAM address bus output line 16 (SRAM) or CAS (DRAM)
RWE
13
O
buffer RAM write enable output
DGND2
14
digital ground 2
RD0
15
I/O
buffer RAM data bus bidirectional line 0
RD1
16
I/O
buffer RAM data bus bidirectional line 1
RD2
17
I/O
buffer RAM data bus bidirectional line 2
RD3
18
I/O
buffer RAM data bus bidirectional line 3
RD4
19
I/O
buffer RAM data bus bidirectional line 4
RD5
20
I/O
buffer RAM data bus bidirectional line 5
RD6
21
I/O
buffer RAM data bus bidirectional line 6
RD7
22
I/O
buffer RAM data bus bidirectional line 7
TEST2
23
I
test input 2
DGND3
24
digital ground 3
TEST1
25
I
test input 1
CROUT
26
O
clock oscillator output
CRIN
27
I
clock oscillator input
SFSY
28
I
serial subcode input frame sync input
RCK
29
O
serial subcode clock output (active LOW)
SUB
30
I
serial input for Q-to-W subcode input
BCK
31
I
serial interface bit clock input
VDDD1
32
digital supply voltage 1 (3.3 V)
WS
33
I
serial interface word clock input
DATA
34
I
serial data input
C2PO
35
I
serial interface flag input
SDA
36
I/O
sub-CPU serial data input/output
SCL
37
I
sub-CPU serial clock input
INT
38
O
sub-CPU open-collector interrupt output
RESET
39
I
power-on reset input (active LOW)
SYN
40
I
sync signal input from sub-CPU


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