 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SAA7385 Datasheet(PDF) 4 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
SAA7385 Datasheet(HTML) 4 Page - NXP Semiconductors |
|
|
4 / 64 page 
1996 Jun 19 4 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 The SAA7385 uses a 33.8688 MHz clock and is capable of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the normal CD-ROM data rate. Third level error correction hardware is included to improve the correction efficiency of the system. The buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the microcontroller to emulate a wait condition when necessary. The SAA7385 comprises five major functional blocks: • The 80C32 microcontroller is an industry standard core • The 53CF94 is an industry standard core • The front-end block connects to the external CD-60 based decoder and fully processes the incoming data stream to provide bytes of data that are stored in the external buffer • The buffer manager block provides the address generation and timing control for the external DRAM buffer • The ECC block performs the error correction functions in hardware on the data in the DRAM buffer. Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application. 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD digital supply voltage 4.5 5.0 5.5 V Tamb operating ambient temperature 0 − 70 °C Tstg storage temperature −55 − +150 °C TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SAA7385GP SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm); body 14 × 20 × 2.8 mm SOT387-2 |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
