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SAA7385 Datasheet(PDF) 39 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 39 Page - NXP Semiconductors

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1996 Jun 19
39
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
11.6
53CF94 related registers
In the 53CF94 SCSI controller, some registers are read only and others are write only. These share the same address
and the multiplexing between the two depends on the read or write select.
This part contains only a brief description of the register definitions. For a more detailed definition, see the data sheet for
the SCSI device.
Table 57 Transfer count registers: 0xF0A4, F0A5 and F0BE- 53CF94 addresses: 0x00, 01, 0E; note 1
Note
1. These registers form the 24-bit transfer count value for DMA operations; they specify the number of bytes that are
transferred.
Table 58 FIFO buffer register: 0xF0A6 - 53CF94 address 0x02; note 1
Note
1. The FIFO is a 16
× 9-bit buffer between the SCSI interface and the memory. The SCSI command packet will be
present in this FIFO ready to be read by the microcontroller at the end of the SCSI command phase.
Table 59 Command register: 0xF0A7 - 53CF94 address 0x03; note 1
Note
1. The command register is a two-deep read/write register used to pass commands to the SCSI controller; up to two
commands can be stacked at the same time. When ENDMA is set, the command is a DMA instruction.
Table 60 Status register and destination ID: 0xF0AC - 53CF94 address 0x04; note 1
Note
1. This register contains the flags indicating the occurrence of certain events.
MNEMONIC
R/W
DATA BYTE
76543210
TCLOW
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
TCMID
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
TCHIGH
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MNEMONIC
R/W
DATA BYTE
76543210
FIFO
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MNEMONIC
R/W
DATA BYTE
76543210
CMD
R/W
ENDMA
COMMAND6 to COMMAND0
MNEMONIC
R/W
DATA BYTE
76543210
STAT
R
INT
GE
PE
TC
VGC
MSG
C/D
I/O
STAT
W
−−−−−
ID2
ID1
ID0


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