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SAA7385 Datasheet(PDF) 36 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 36 Page - NXP Semiconductors

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1996 Jun 19
36
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
Table 51 Last complete frame number: 0xF0E6, F0E7
11.3
ECC to buffer manager interface
The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides
an offset address and uses a frame address programmed by the microcontroller, ECCFRM#. The logic can write a single
byte or variable number of bytes. In the event of an access to a variable number of bytes, the ECC logic will assert the
signal BURST and EREQ to indicate that a large number of cycles are requested. For each read or write cycle, the buffer
manager will toggle EACK HIGH for one clock cycle to indicate that one byte of data has been read from or written to the
memory. A single byte cycle will be the same with the exception that BURST will remain negated (LOW). In the event of
a higher priority memory access request during a burst cycle, EACK will remain LOW for the duration of the higher priority
access cycle. At the end of the higher priority access, the burst cycle will resume and EACK will again toggle HIGH after
each read or write is completed.
Table 52 ECC frame number address registers: 0xF0F4, F0F5; notes 1 and 2
Notes
1. These registers provide the frame number address for ECC access to memory. The counter associated with these
registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure
that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the
update will be delayed until the access is completed.
2. ECCFRM# is used to determine the frame address for all ECC operations. This register must be reloaded for each
frame accessed by the ECC.
MNEMONIC
R/W
DATA BYTE
76543210
LSTCMPFM
R
NUM7
NUM6
NUM5
NUM4
NUM3
NUM2
NUM1
NUM0
LSTCMPFM
R
−−−−−−−
NUM8
MNEMONIC
R/W
DATA BYTE
76543210
ECCFRM#
R/W
NUM7
NUM6
NUM5
NUM4
NUM3
NUM2
NUM1
NUM0
ECCFRM#
R/W
−−−−−−−
NUM8
11.4
SCSI to buffer manager interface
The SCSI registers should be loaded prior to starting an
SCSI transfer. The SCSIMOD register should be loaded
first. BYT/PAG from this register is used to control the type
of DRAM access used by the SCSI interface. If BYT/PAG
is HIGH then burst mode access cycles are selected;
multiple CAS access cycles are used to access data as
fast as possible. RD_BUF from SCSIMOD controls the
direction of data flow to the buffer memory; this bit is kept
LOW to allow reading of data from the DRAM buffer. If
RD_BUF is asserted then SCSI data will be written to the
DRAM buffer. OFF_ADR from SCSIMOD is used to select
between one and two offset mode for the SCSI transfer.
OFF_ADR LOW selects single offset mode in which one
block of data is transferred for each frame of the buffer.
The transfer block is specified by registers SCSIOFFS and
SCSIOFFE. For each frame, the transfer will start at the
address specified by SCSIOFFS and continue until the
address specified by SCSIOFFE is transferred. After each
block is transferred, the frame address SCSICFRM will be
incremented and the transfer will continue with the same
address block from the next frame. If OFF_ADR is set,
then two blocks of data are transferred. In the two offset
mode, both SCSIOFFS and SCSIOFFE are used to
access two independent register pairs; for simplicity, these
are called the A registers and the B registers. In this event,
the transfer for each frame is a two step process.
First, the offset block specified by SCSIOFFS-A and
SCSIOFFE-A is transferred; the transfer address range is
from SCSIOFFS-A to SCSIOFFE-A and includes both the
start and end addresses. After the first offset block is


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