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SAA7385 Datasheet(PDF) 27 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 27 Page - NXP Semiconductors

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1996 Jun 19
27
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
9.1
S2B UART registers
This section describes the registers used for the S2B UART control.
Table 28 S2B UART transmit, receive and status buffer: 0xF0A1, F0A2 and F0A3
Note
1. WTS2B is for the transmit data byte from the S2B UART and RDS2B is for the receive data byte from the S2B UART.
Table 29 S2BSTAT field description
Table 30 Baud rate generator control: 0xF0C0; note 1
Note
1. Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over
the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel
information.
MNEMONIC
R/W
DATA BYTE
76543210
WTS2B(1)
W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
RDS2B
R
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
S2BSTAT
R
−−
SPR
CPR
TXDRDY
PE
OVRRUN
RXDRDY
FIELD
DESCRIPTION
RXDRDY
A logic 1 indicates that the receive data is valid.
OVRRUN
A logic 1 indicates that the data in the receive buffer was not read before it was over written by the next
byte.
PE
A logic 1 indicates that a parity error was detected in the receive data byte; this is usually caused by the
wrong baud rate.
TXDRDY
A logic 1 indicates that the transmit data buffer is empty and ready for another byte.
CPR
S2B handshake bit which may be interpreted as ‘clear to send’; this is generated automatically by the
UART. It is asserted whenever the UART receiver is ready for a byte and negated as soon as the stop
bit is shifted in. It is again asserted as soon as the received byte is read by the 80C32.
SPR
S2B handshake bit which may be interpreted as ‘request to send’; this is received from the CD-ROM
engine UART transmitter and will generate an interrupt to the 80C32 if the TXRDY bit is set and the
interrupt is not masked.
MNEMONIC
R/W
DATA BYTE
7
654
3
2
1
0
BRGSEL
R/W
C_34_16
LOCK
EVENPAR INVSUBC
INVQ
ICESEL1
ICESEL0


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