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SAA7385 Datasheet(PDF) 26 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 26 Page - NXP Semiconductors

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1996 Jun 19
26
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
Table 25 RDJMPRS field description
Table 26 General purpose bits: 0xF0C2; note 1
Note
1. Register 0xF0C2 controls the direction and output state of the general purpose I/O bits on the SAA7385. Reading
the GPIO direction bits reflects the last value that was written to the register. The four GPIO data bits shows the
current value of the input signals in the input mode. In the output mode, the last value written to the output latches is
that which is read back.
Table 27 GPIOCTL field description
FIELD
DESCRIPTION
JUMPER7 to JUMPER0
Indicates the value of the DRAM data bus on power-up. The data bus may be pulled HIGH
or LOW using weak pull-ups and pull-downs hence up to eight jumper settings are
accommodated.
MNEMONIC
R/W
DATA BYTE
76543210
GPIOCTL
R/W
GPDAT4
GPDIR4
GPDAT3
GPDIR3
GPDAT2
GPDIR2
GPDAT1
GPDIR1
FIELD
DESCRIPTION
GPDIR1
General purpose bit direction control. Default LOW puts GPIO1 into the input mode, setting this HIGH
puts GPIO1 in output mode.
GPDAT1
GPIO1 data bit.
GPDIR2
General purpose bit direction control. Default LOW puts GPIO2 into the input mode, setting this HIGH
puts GPIO2 in output mode.
GPDAT2
GPIO2 data bit.
GPDIR3
General purpose bit direction control. Default LOW puts GPIO3 into the input mode, setting this HIGH
puts GPIO3 in output mode.
GPDAT3
GPIO3 data bit.
GPDIR4
General purpose bit direction control. Default LOW puts GPIO4 into the input mode, setting this HIGH
puts GPIO4 in output mode.
GPDAT4
GPIO4 data bit.


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