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SAA7385 Datasheet(PDF) 24 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 24 Page - NXP Semiconductors

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1996 Jun 19
24
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
9
FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS
This chapter describes the various SAA7385 control signals; front panel and basic engine signals, jumper settings and
use of the general purpose signals.
Table 16 Start clock doubler: 0xF091
A write of any value to this address will engage the clock doubler. The state of the doubler may be obtained by reading
C_34_16 in BRGSEL (see Table 30). If this bit is set then the clock doubler is engaged. On power-on, the clock doubler
is disabled. Once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, a SCSI
reset or a reset from the watch-dog timer. The clock doubler must not be engaged when a 33.8688 MHz clock is
connected to OSCIN (pin 117).
Table 17 Frequency synthesizer test register: 0xF0D8; note 1
Note
1. Register 0xF0D8 is used for IC-level testing and to power down the frequency synthesizer. Only bit USE_IN should
be asserted in normal operation.
Table 18 FSTEST field description
Table 19 Disconnected pulse-width modulator control: 0xF0B3; note 1
Note
1. Register 0xF0B3 is disconnected.
MNEMONIC
R/W
DATA BYTE
76543210
CLKSEL
W
−−−−−−−−
MNEMONIC
R/W
DATA BYTE
7
6
5432
1
0
FSTEST
R/W
−−
USE_IN
CPSEL
FVCOD
FS_LOCK
−−
FIELD
LOGIC
DESCRIPTION
FS_LOCK
0
normal operation
1
3-state LED and switch LQDATA to FS_LOCK
FVCOD
0
normal operation
1
test mode for FVCOD from the synthesizer
CPSEL
0
normal operation
1
test mode for CPSEL from the synthesizer
USE_IN
0
use internal synthesizer
1
power down the synthesizer and operate off a 33.87 MHz input clock
MNEMONIC
R/W
DATA BYTE
76543210
WTPWM
R/W
−−−−−−−−


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