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SAA7385 Datasheet(PDF) 21 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 21 Page - NXP Semiconductors

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1996 Jun 19
21
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
Table 10 INTRFLG field descriptions
8.4
Microcontroller RAM organization
MICFRM# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to
0x8FFF. To obtain the actual byte location within the buffer RAM, the lower 12 bits of the microcontroller address form
the relative offset and hence the absolute address is found.
Note that the microcontroller has the option of addressing memory in a linear fashion using the 32 kbyte address space
between 0x000 and 0x7FFF. If this 32 kbyte page is used, the PAGEREG must be programmed with the required page
address. PAGEREG is used to select the required page when the microcontroller makes a linear access to the buffer
memory using the address space 0x7000 to 0x7FFF. The actual address is the fifteen LSBs from the microcontroller plus
32768 times the value in PAGEREG.
Table 11 Microcontroller frame number address registers: 0xF0F6 and 0xF0F7
Registers 0xF0F6 and 0xF0F7 provide the frame number address for the microcontroller access to memory. The counter
associated with these registers is loaded after the most significant byte is written; the least significant byte must be written
first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the
counter, the update will be delayed until the access is complete.
FIELD
DESCRIPTION
FRM_STR
set one when one complete frame is stored
STR_LST
set at the start of the last frame
FE_2352
set if the front-end data exceeds 2352 bytes
FE_HDR
front-end interrupt for header (or Q channel) ready
ECC_COR
ECC interrupt for correction complete
RFERXINT
front-end interrupt for receive ready
FETXINT
front-end interrupt for transmit ready
MNEMONIC
R/W
DATA BYTE
76543210
MICFRM#
R/W
NUM7
NUM6
NUM5
NUM4
NUM3
NUM2
NUM1
NUM0
MICFRM#
R/W
−−−−−−−
NUM8


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