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SAA7385 Datasheet(PDF) 20 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 20 Page - NXP Semiconductors

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1996 Jun 19
20
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
Table 7
Command execution times
All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q
corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other
buffer traffic, and configuration of nibble-wide memory.
8.3.1
INTERRUPT REGISTER DEFINITIONS
Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be
enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output
latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt,
the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the
interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any
bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still
detect the occurrence because the event is still posted in INTRFLG.
Table 8
Interrupt mask register: 0xF0FB
Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an
interrupt, the bit in this register must be set HIGH.
Table 9
Interrupt flag register: 0xF0FC
If any bit is set in this register (Table 9) then an interrupt may be sent to the microcontroller. Table 10 shows when the
interrupts are asserted; assuming the corresponding mask bit is set.
COMMAND
CYCLES
TIME (
µs)
at 33 MHz
MEMORY
ACCESSES
CALCULATE_SYNDROMES (not Mode 2, Form 1)
5604
186.8
2658
CALCULATE_SYNDROMES (Mode 2, Form 1)
5600
186.7
2654
CRC_RECALCULATE (not Mode 2, Form 1)
4136
137.9
2068
CRC_RECALCULATE (Mode 2, Form 1)
4120
137.3
2060
COPY_RESULTS (not Mode 2, Form 1)
1148
38.3
574
COPY_RESULTS (Mode 2, Form 1)
1156
38.5
578
CORRECT_P_SYNDROMES
(maximum addition per correction)
1466
157
48.9
5.2
0
2
CORRECT_Q_SYNDROMES
(maximum addition per correction)
888
167
29.6
5.6
0
2
TEST_ECC_RAM_READ
1184
39.5
592
TEST_ECC_RAM_WRITE
1184
39.5
592
MNEMONIC
R/W
DATA BYTE
76543210
INTRMSK
R/W
MASK7
MASK6
MASK5
MASK4
MASK3
MASK2
MASK1
MASK0
MNEMONIC
R/W
DATA BYTE
7
6
5
4
321
0
INTRFLG
R/W
FETXINT
FERXINT
ECC_COR FE_HDR
FE2352
STR_LST FRM_STR


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