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SAA7385 Datasheet(PDF) 11 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 11 Page - NXP Semiconductors

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1996 Jun 19
11
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
7
FUNCTIONAL DESCRIPTION
7.1
80C32 microcontroller
The standard specification for details of the operation for
this part may be found in any data sheet covering the
80C32 microcontroller. The one deviation from a normal
80C32 is the addition of all of the control registers for the
special function register map for the 80C32. All of the
SAA7385 control registers, including the 53CF94 control
registers appear within this space.
7.2
53CF94 fast SCSI controller
The details of operation of this block may be found in the
“53CF94 data manual”. Two deviations from the operation
of a normal 53CF94 have been made. The first is that the
part supports single-ended SCSI bus operation only.
The second deviation is the additional feature of mapping
the control registers into the 80C32 special function
register map as previously mentioned.
7.3
Input clock doubler
To facilitate compatibility of the SAA7385 with the
maximum number of CD decoders, a clock doubler has
been included. This clock doubler may take a
16.9344 MHz clock and double this when requested to do
so by the microcontroller. Logic has been included to
remove the possibility of a ‘runt’ clock pulse when the
doubler is engaged. Once engaged, the only way to
disengage it is via a reset condition.
7.4
Front-end
The front-end is comprised of many sub-sections.
7.4.1
BLOCK DECODER
The block decoder first reverses the bits of each received
byte and then runs them through a linear feedback shift
register to be de-scrambled. The polynomial used to
de-scramble the serial data is as follows: X15 +X+1
It also detects and tests the synchronization field and will
start the data clock when commanded. The de-scrambled
header is assembled into four registers (MODE, MINS,
SECS and FRMS) with header ready and header error
status (see HDRRDY and HDRERR in RDDSTAT).
The data clock does not have to be enabled to receive
valid headers.
Also included in this section is the logic required to decide
when to start collecting data and sub-code information
taken from the synchronization signal.
7.4.2
SECTOR SEQUENCER
The sector sequencer de-serializes the data and error
flags from the block decoder and determines when to:
• Write data to the buffer
• Write flags to the buffer
• Test the header to determine the Mode
• Test the sub-header to determine the Form
• Test the CRC
• End the sector and write the status byte to the buffer.
Included in the sector sequencer is the CRC generator
which checks each Yellow Book or Green Book sector as
it is shifted into the SAA7385 in accordance with the
following polynomial:
X32 +X31 +X16 +X15 +X4 +X3 +X+1
The status of each sector is saved and written to the buffer
at the end of the sector.
7.4.3
SUB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR
A UART which samples asynchronous bits on a 24 clocks
per bit basis is included. This is required because Philips
decoders output the sub-code data at nominally 24 clocks
per bit, but not synchronized to the data. Also included is a
sub-code synchronization detector which senses the
beginning of each new sector of sub-code information.
The serial sub-code information is assembled into bytes in
the following order:
Data bits 7 to 0 = 0, Q, R, S, T, U, V and W.
As each byte is assembled, it is sent to the buffer manager
to be written to the DRAM buffer. At the same time, the
Q-channel bits are assembled into bytes and sent to the
buffer. All Q-channel bytes except CRC are sorted in
registers for use by the microcontroller. The track, mode,
minutes, seconds and frames bytes (RDTK, RDMD,
RDMN, RDSC and RDFM) are also stored in registers for
use by the microcontroller. The Q-channel CRC (last two
bytes) is checked just before the end of the sub-code
sector. If the CRC check fails, BADQ in RDDSTAT is
available to the microcontroller and is written into the buffer
at the end of the sector. When the five Q-channel registers
have been updated, QFRMRDY in RDDSTAT is set.
The five Q-channel registers are valid while QFRMRDY is
set. In the audio mode, HDRRDY in RDDSTAT generates
this interrupt, but the QFRMRDY bit will still be available as
status to the microcontroller.


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