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SAA7385 Datasheet(PDF) 41 Page - NXP Semiconductors

Part No. SAA7385
Description  Error correction and host interface IC for CD-ROM SEQUOIA
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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SAA7385 Datasheet(HTML) 41 Page - NXP Semiconductors

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1996 Jun 19
41
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
Table 65 SEQSTP field descriptions
Table 66 FIFO flags and synchronous offset register: 0xF0AF - 53CF94 address 0x07; note 1
Note
1. The field description for the FIFO flags register is shown in Table 67.
Table 67 FIFOFLG field descriptions
Table 68 Configuration registers: 0xF0B4, F0B7, F0BC and F0BD - 53CD94 addresses 0x08, 0B, 0C and 0D; note 1
Note
1. The registers described allows the controller to be configured for the specific mode of operation.
FIELD
DESCRIPTION
SS2 to SS0
Sequence step. Counter increments at various points in a command; may be used for error
recovery.
SOM
Synchronous offset maximum. When clear, the synchronous offset has reached the maximum
value.
TRANSPERIOD Synchronous transfer period. Specifies minimum time between successive REQ or ACK pulses.
MNEMONIC
R/W
DATA BYTE
76543210
FIFOFLG
R
SS2
SS1
SS0
FF4
FF3
FF2
FF1
FF0
FIFOFLG
W
SYNCOFFSET7 to SYNCOFFSET0
FIELD
DESCRIPTION
FF
number of bytes in the FIFO
SS
duplicates of sequence step register
SYNCOFFSET
controls handshaking in synchronous transfer mode
MNEMONIC
R/W
DATA BYTE
76543210
CONFIG1
R/W
SLOW
SRD
PTEST
PCHK
CTEST
MYBUSID2 to MYBUSID0
CONFIG2
R/W
RFB
FE
EBC
DHZ
SCSI2
BPA
RPE
DPE
CONFIG3
R/W
IMRC
QTE
CDB10
FSCSI
FCLK
SRB
ADMA
T8
CONFIG4
R/W
−−−−−
EAN
TEST
BBTE


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