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SAA7370 Datasheet(PDF) 51 Page - NXP Semiconductors |
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SAA7370 Datasheet(HTML) 51 Page - NXP Semiconductors |
51 / 60 page 1998 Feb 26 51 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7370 Notes 1. The 4-wire bus mode microprocessor interface timing for writing to registers 0 to F, and reading Q-channel subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data rate is lower. 2. Negative set-up time means that the data may change after clock transition. WRITE MODE (CL = 20 pF) tsD set-up time SDA to SCL 0 − 0 − ns thD hold time SCL to SDA 950 − 950 − ns tsCL set-up time SCL to SILD 480 − 480 − ns thCL hold time SILD to SCL 120 − 120 − ns tdPLP delay between two SILD pulses 70 − 70 −µs tdWZ delay time SDA high-impedance to SILD 0 − 0 − ns SYMBOL PARAMETER CONDITIONS NORMAL MODE LOCK-TO-DISC MODE UNIT MIN. MAX. MIN. MAX. handbook, full pagewidth tW(SBSY) tW(SFSY) tr VDD – 0.8 V VDD – 0.8 V tSFSYL tSFSYH Tcy(block) tcy(frame) tf td(SFSY−RCK) td(SFSY−SUB) th(RCK−SUB) td(RCK−SUB) SBSY SFSY RCK SUB SFSY (4-wire mode) SFSY (3-wire mode) 0.8 V 0.8 V 0.8 V MBG414 Fig.31 Subcode interface timing diagram. |
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