DS89C420 Ultra-High-Speed Microcontroller

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Note 1:

The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/

following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot

exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.

External Clock Speed

4X/

2X

CD1

CD0

Number of External Clock

Cycles per System Clock

Min

Max

1

0

0

1/4

5MHz

8.25MHz

0

0

0

1/2

10MHz

16.5MHz

X

0

1

Reserved

—

—

X

1

0

1

See AC Characteristics

See AC Characteristics

X

1

1

1024

See AC Characteristics

See AC Characteristics

Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms

MD2

MD1

MD0

MOVX INSTRUCTION TIME

(MACHINE CYCLES)

0

0

0

2

0

0

0

0

0

0

0

1

3

2

1

0

0

1

0

1

0

4

6

1

0

0

1

0

1

1

5

10

1

0

0

1

1

0

0

9

14

5

4

1

1

1

0

1

10

18

5

4

1

1

1

1

0

11

22

5

4

1

1

1

1

1

12

26

5

4

1

1

Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE,

PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load

capacitance is dependent on the frequency of the selected crystal.

Figure 1. Non-Page Mode Timing

ALE

Port 0

Port 2

LSB

DATA

XTAL1

PSEN

RD

MSB

MSB

MSB

MSB

MSB

WR

LSB

LSB

LSB

LSB

DATA

MOVX

MOVX

OPCODE