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SAA7325 Datasheet(PDF) 11 Page - NXP Semiconductors

Part # SAA7325
Description  Digital servo processor and Compact Disc decoder with integrated DAC CD10
Download  68 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA7325 Datasheet(HTML) 11 Page - NXP Semiconductors

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1999 Jun 17
11
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10)
SAA7325
Fig.6 Data slicer showing typical application components.
47 pF
HFREF
HFIN
ISLICE
22 k
2.2 k
100 nF
100 nF
1 nF
HF input
crystal
clock
DQ
DPLL
VSSA
VSSA
VSS
MGS179
VDD
100
µA
100
µA
7.4
Demodulator
7.4.1
FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
• A sync coincidence is detected; sync pattern occurs
588
±1 EFM clocks after the previous sync pattern
• A new sync pattern is detected within ±6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found. The PLL
lock signal can be accessed via the SDA or STATUS pins
selected by decoder registers 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2
EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.


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