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SAA7324 Datasheet(PDF) 43 Page - NXP Semiconductors |
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SAA7324 Datasheet(HTML) 43 Page - NXP Semiconductors |
43 / 68 page 2000 Jun 26 43 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II) SAA7324 Table 15 Loop filter bandwidth Note 1. The initial column shows the Power-on reset state. 7.15.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS Table 16 Shadow register settings REGISTER ADDRESS DATA FUNCTION INITIAL(1) LOOP BANDWIDTH (HZ) INTERNAL BANDWIDTH (HZ) LOW-PASS BANDWIDTH (HZ) 8 (PLL loop filter bandwidth) 1000 0000 1640 × n 525 × n 8400 × n − 0001 3279 × n 263 × n 16800 × n − 0010 6560 × n 131 × n 33600 × n − 0100 1640 × n 1050 × n 8400 × n − 0101 3279 × n 525 × n 16800 × n − 0110 6560 × n 263 × n 33600 × n − 1000 1640 × n 2101 × n 8400 × n − 1001 3279 × n 1050 × n 16800 × n reset 1010 6560 × n 525 × n 33600 × n − 1100 1640 × n 4200 × n 8400 × n − 1101 3279 × n 2101 × n 16800 × n − 1110 6560 × n 1050 × n 33600 × n − SHADEN BIT SHADOW REGISTER ADDRESS DATA FUNCTION INITIAL 13 control of versatile and clock pins 0011 XXX0 select CL4 on CL11/4 output reset XXX1 select CL11 on CL11/4 output − XX0X enable CL11/4 output pin reset XX1X set CL11/4 output pin to high-impedance − X0XX enable CL16 output pin reset X1XX set CL16 output pin to high-impedance − 0XXX V2/V3 pin configured as V2 input reset 1XXX V2/V3 pin configured as V3 output (open-drain) − |
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