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SAA7191B Datasheet(PDF) 5 Page - NXP Semiconductors

Part # SAA7191B
Description  Digital Multistandard Colour Decoder, Square Pixel DMSD-SQP
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA7191B Datasheet(HTML) 5 Page - NXP Semiconductors

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August 1996
5
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
SAA7191B
6
PINNING
SYMBOL
PIN
DESCRIPTION
SP
1
connected to ground (shift pin for testing)
AP
2
connected to ground (action pin for testing)
RESN
3
reset, active LOW
CREF
4
clock reference, sync from external to ensure in-phase signals on the YUV-bus
VDD1
5
+5 V supply input 1
CHR0
6
chrominance input data bits CHR7 to CHR0
from a Y/C (VHS, Hi8) source in two’s complement format
CHR1
7
CHR2
8
CHR3
9
CHR4
10
CHR5
11
CHR6
12
CHR7
13
CVBS0
14
luminance respectively CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)
CVBS1
15
CVBS2
16
CVBS3
17
VDD2
18
+5 V supply input 2
VSS1
19
ground 1 (0 V)
CVBS4
20
luminance respectively CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)
CVBS5
21
CVBS6
22
CVBS7
23
GPSW1
24
Port 1 output for general purpose (programmable)
GPSW2
25
Port 2 output for general purpose (programmable)
HCL
26
black level clamp pulse (programmable), e.g. for TDA8708 (ADC)
LLC
27
line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system)
VDD3
28
+5 V supply input 3
HSY
29
horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC)
VS
30
vertical sync output signal
HS
31
horizontal sync output signal (programmable)
HL
32
horizontal lock flag, HIGH = PLL locked
XTAL
33
26.8 MHz clock output
XTALI
34
26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave)
VSSA
35
analog ground
LFCO
36
line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz)
VDDA
37
+5 V supply input for analog part
VSS2
38
ground 2 (0 V)
ODD
39
odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1
SDA
40
I2C-bus data line


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