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SAA7146A Datasheet(PDF) 60 Page - NXP Semiconductors |
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SAA7146A Datasheet(HTML) 60 Page - NXP Semiconductors |
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60 / 144 page  1998 Apr 09 60 Philips Semiconductors Product specification Multimedia bridge, high performance Scaler and PCI circuit (SPCI) SAA7146A Table 52 Protection bits BIT NUMBER FUNCTION FIXED 1 F V H P3 P2 P1 P0 711111111 600001101 500110011 401010101 301100110 201011010 100111100 001101001 7.8.5 SYNCHRONIZATION SIGNALS Horizontal, vertical and frame synchronization signals are either carried beside the data stream on the extra sync pins of DD1 (one pair of sync pins per D1 channel) or are encoded as SAV and EAV in the 8-bit wide video signal stream. For the 16-bit wide YUV stream sync signals are always available on separate pins. For D1 video inputs the SAA7146A is programmed to determine where to recover the synchronization information (from the dedicated sync pins or from the encoded SAV and EAV codes in the data stream). For D1 video outputs, the SAA7146A can be programmed to deliver synchronization information both in SAV and EAV codes as well as on the dedicated sync pins. Non-standard rastered video signals are supported by sync signals at the dedicated sync pins as well as via SAV and EAV codes. The number of clock cycles, pixels per line and lines per field can be non-standard. These number can range from 1 up to 4095. The signal at the HS pin can perform the following functions: • HS: input only, the rising edge is selected to act as timing reference • HREF: input only, gated with CREF, the rising edge is selected as timing reference • HGT: I/O, HIGH during active video • ACT input only: HIGH during active video, inactive during horizontal and vertical blanking • HGT and ACT: envelope all active pixels (there is no active pixel outside HGT or ACT), but may also include clock cycles marked as not valid pixels by means of PXQ. The vertical sync signal can perform the following functions: • VS: input only positive or negative, one edge is selected as timing reference: – If selected edge of VS and selected edge of HS are in phase, then begin 1st (odd) field – If selected edges of VS and HS are out of phase, then begin 2nd (even) field. • V-DMSD: input only, falling (trailing) edge is timing reference: – If falling edge of V-DMSD is in high phase of HREF, then begin 1st (odd) field – If falling edge of V-DMSD is in low phase of HREF, then begin 2nd (even) field. • VGT: I/O, HIGH during active video, (no holes for horizontal blanking) • FS: input only, positive or negative, frame sync, (odd/even), (313/312, 263/262 lines) HIGH in one field, LOW in the other, changes on full line boundaries only. 7.8.6 FIELD DETECTION The fields are detected simultaneously at both D1 sync inputs. The results are available in two status registers. |
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