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SAA7128H Datasheet(PDF) 18 Page - NXP Semiconductors |
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SAA7128H Datasheet(HTML) 18 Page - NXP Semiconductors |
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18 / 56 page  2000 Mar 08 18 Philips Semiconductors Product specification Digital video encoder SAA7128H; SAA7129H Table 8 Subaddress 28H Table 9 Subaddress 29H Table 10 Subaddress 2AH Table 11 Subaddress 2BH BIT SYMBOL DESCRIPTION 7 DECCOL 0 = disable colour detection bit of RTCI input 1 = enable colour detection bit of RTCI input; bit RTCE must be set to logic 1 (see Fig.22) 6 DECFIS 0 = field sequence as FISE in subaddress 61 1 = field sequence as FISE bit in RTCI input; bit RTCE must be set to logic 1 (see Fig.22) 5 BS5 starting point of burst in clock cycles 4 BS4 PAL: BS[5:0] = 33 (21H); default value after reset NTSC: BS[5:0] = 25 (19H) 3 BS3 2 BS2 1 BS1 0 BS0 BIT SYMBOL DESCRIPTION 7 − These 2 bits are reserved; each must be set to logic 0. 6 − 5 BE5 ending point of burst in clock cycles PAL: BE[5:0] = 29 (1DH); default value after reset NTSC: BE[5:0] = 29 (1DH) 4 BE4 3 BE3 2 BE2 1 BE1 0 BE0 BIT SYMBOL DESCRIPTION 7 to 0 CG[07:00] LSB of the byte is encoded immediately after run-in, the MSB of the byte has to carry the CRCC bit, in accordance with the definition of copy generation management system encoding format. BIT SYMBOL DESCRIPTION 7 to 0 CG[15:08] Second byte; the MSB of the byte has to carry the CRCC bit, in accordance with the definition of copy generation management system encoding format. |
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